Lines Matching +full:r600 +full:- +full:-
1 //===- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
16 #include "R600.h"
67 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() &&
71 if (!ST->hasCFAluBug())
76 case R600::CF_ALU_PUSH_BEFORE:
77 case R600::CF_ALU_ELSE_AFTER:
78 case R600::CF_ALU_BREAK:
79 case R600::CF_ALU_CONTINUE:
82 if (ST->getWavefrontSize() == 64) {
83 // We are being conservative here. We only require this work-around if
89 // work-around when CurrentSubEntries > 3 allows us to over-allocate stack
93 assert(ST->getWavefrontSize() == 32);
94 // We are being conservative here. We only require the work-around if
108 assert(!ST->hasCaymanISA());
109 if (ST->getGeneration() <= AMDGPUSubtarget::R700) {
116 // sub-entry for the first non-WQM push.
121 assert(ST->getGeneration() >= AMDGPUSubtarget::EVERGREEN);
138 case R600::CF_PUSH_EG:
139 case R600::CF_ALU_PUSH_BEFORE:
141 if (!ST->hasCaymanISA() &&
147 ST->getGeneration() > AMDGPUSubtarget::EVERGREEN &&
148 !ST->hasCaymanISA() &&
174 CurrentEntries--;
176 CurrentSubEntries-= getSubEntrySize(Top);
181 CurrentEntries--;
210 case R600::KILL:
211 case R600::RETURN:
220 bool isEg = (ST->getGeneration() >= AMDGPUSubtarget::EVERGREEN);
223 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600;
226 Opcode = isEg ? R600::CF_VC_EG : R600::CF_VC_R600;
229 Opcode = isEg ? R600::CF_CALL_FS_EG : R600::CF_CALL_FS_R600;
232 Opcode = isEg ? R600::WHILE_LOOP_EG : R600::WHILE_LOOP_R600;
235 Opcode = isEg ? R600::END_LOOP_EG : R600::END_LOOP_R600;
238 Opcode = isEg ? R600::LOOP_BREAK_EG : R600::LOOP_BREAK_R600;
241 Opcode = isEg ? R600::CF_CONTINUE_EG : R600::CF_CONTINUE_R600;
244 Opcode = isEg ? R600::CF_JUMP_EG : R600::CF_JUMP_R600;
247 Opcode = isEg ? R600::CF_ELSE_EG : R600::CF_ELSE_R600;
250 Opcode = isEg ? R600::POP_EG : R600::POP_R600;
253 if (ST->hasCaymanISA()) {
254 Opcode = R600::CF_END_CM;
257 Opcode = isEg ? R600::CF_END_EG : R600::CF_END_R600;
261 return TII->get(Opcode);
275 if (R600::R600_Reg128RegClass.contains(Reg))
278 DstMI = TRI->getMatchingSuperReg(Reg,
279 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)),
280 &R600::R600_Reg128RegClass);
284 if (R600::R600_Reg128RegClass.contains(Reg))
287 SrcMI = TRI->getMatchingSuperReg(Reg,
288 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)),
289 &R600::R600_Reg128RegClass);
305 bool IsTex = TII->usesTextureCache(*ClauseHead);
312 if ((IsTex && !TII->usesTextureCache(*I)) ||
313 (!IsTex && !TII->usesVertexCache(*I)))
323 .addImm(AluInstCount - 1); // COUNT
329 R600::ALU_LITERAL_X,
330 R600::ALU_LITERAL_Y,
331 R600::ALU_LITERAL_Z,
332 R600::ALU_LITERAL_W
335 TII->getSrcs(MI);
337 if (Src.first->getReg() != R600::ALU_LITERAL_X)
342 return val->isImm() && (val->getImm() == Imm);
347 TII->getOperandIdx(MI.getOpcode(), R600::OpName::literal));
351 unsigned Index = It - Lits.begin();
352 Src.first->setReg(LiteralRegs[Index]);
356 Src.first->setReg(LiteralRegs[Lits.size()]);
365 MachineBasicBlock *MBB = InsertPos->getParent();
369 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
370 TII->get(R600::LITERALS))
388 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
391 if (I->isBundle()) {
394 while (++BI != E && BI->isBundledWithPred()) {
395 BI->unbundleFromPred();
396 for (MachineOperand &MO : BI->operands()) {
411 MachineInstrBuilder MILit = BuildMI(MBB, I, I->getDebugLoc(),
412 TII->get(R600::LITERALS));
413 if (Literals[i]->isImm()) {
414 MILit.addImm(Literals[i]->getImm());
416 MILit.addGlobalAddress(Literals[i]->getGlobal(),
417 Literals[i]->getOffset());
420 if (Literals[i + 1]->isImm()) {
421 MILit.addImm(Literals[i + 1]->getImm());
423 MILit.addGlobalAddress(Literals[i + 1]->getGlobal(),
424 Literals[i + 1]->getOffset());
432 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1);
440 MachineBasicBlock *BB = Clause.first->getParent();
441 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount);
443 BB->splice(InsertPos, BB, MI);
449 Clause.first->getOperand(0).setImm(0);
451 MachineBasicBlock *BB = Clause.first->getParent();
452 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount);
454 BB->splice(InsertPos, BB, MI);
475 MaxFetchInst = ST->getTexVTXClauseSize();
476 TII = ST->getInstrInfo();
477 TRI = ST->getRegisterInfo();
499 if (TII->usesTextureCache(*I) || TII->usesVertexCache(*I)) {
500 LLVM_DEBUG(dbgs() << CfCount << ":"; I->dump(););
508 if (MI->getOpcode() != R600::ENDIF)
510 if (MI->getOpcode() == R600::CF_ALU)
514 CFStack.requiresWorkAroundForInst(MI->getOpcode());
515 switch (MI->getOpcode()) {
516 case R600::CF_ALU_PUSH_BEFORE:
519 << "Applying bug work-around for ALU_PUSH_BEFORE\n");
520 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(R600::CF_PUSH_EG))
523 MI->setDesc(TII->get(R600::CF_ALU));
525 CFStack.pushBranch(R600::CF_PUSH_EG);
527 CFStack.pushBranch(R600::CF_ALU_PUSH_BEFORE);
529 case R600::CF_ALU:
532 LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump(););
535 case R600::WHILELOOP: {
544 MI->eraseFromParent();
548 case R600::ENDLOOP: {
556 MI->eraseFromParent();
560 case R600::IF_PREDICATE_SET: {
567 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
568 MI->eraseFromParent();
572 case R600::ELSE: {
580 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
582 MI->eraseFromParent();
586 case R600::ENDIF: {
596 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
603 IfOrElseInst->getOperand(1).setImm(1);
605 MI->eraseFromParent();
608 case R600::BREAK: {
614 MI->eraseFromParent();
617 case R600::CONTINUE: {
622 MI->eraseFromParent();
626 case R600::RETURN: {
631 BuildMI(MBB, I, DL, TII->get(R600::PAD));
634 MI->eraseFromParent();
642 if (TII->isExport(MI->getOpcode())) {
643 LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump(););
651 TII->get(R600::CF_ALU_POP_AFTER))
652 .addImm(Alu->getOperand(0).getImm())
653 .addImm(Alu->getOperand(1).getImm())
654 .addImm(Alu->getOperand(2).getImm())
655 .addImm(Alu->getOperand(3).getImm())
656 .addImm(Alu->getOperand(4).getImm())
657 .addImm(Alu->getOperand(5).getImm())
658 .addImm(Alu->getOperand(6).getImm())
659 .addImm(Alu->getOperand(7).getImm())
660 .addImm(Alu->getOperand(8).getImm());
661 Alu->eraseFromParent();
663 MFI->CFStackSize = CFStack.MaxStackSize;
670 return "R600 Control Flow Finalizer Pass";
677 "R600 Control Flow Finalizer", false, false)
679 "R600 Control Flow Finalizer", false, false)