Lines Matching +full:r600 +full:- +full:-
1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// R600 Implementation of TargetInstrInfo.
12 //===----------------------------------------------------------------------===//
32 : R600GenInstrInfo(-1, -1), RI(), ST(ST) {}
44 if ((R600::R600_Reg128RegClass.contains(DestReg) ||
45 R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
46 (R600::R600_Reg128RegClass.contains(SrcReg) ||
47 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) {
49 } else if((R600::R600_Reg64RegClass.contains(DestReg) ||
50 R600::R600_Reg64VerticalRegClass.contains(DestReg)) &&
51 (R600::R600_Reg64RegClass.contains(SrcReg) ||
52 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) {
59 buildDefaultInstruction(MBB, MI, R600::MOV,
66 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV,
68 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0))
76 for (const MachineOperand &MO : MBBI->all_uses())
86 case R600::MOV:
87 case R600::MOV_IMM_F32:
88 case R600::MOV_IMM_I32:
100 case R600::CUBE_r600_pseudo:
101 case R600::CUBE_r600_real:
102 case R600::CUBE_eg_pseudo:
103 case R600::CUBE_eg_real:
131 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1;
140 case R600::PRED_X:
141 case R600::INTERP_PAIR_XY:
142 case R600::INTERP_PAIR_ZW:
143 case R600::INTERP_VEC_LOAD:
144 case R600::COPY:
145 case R600::DOT_4:
155 return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
163 return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
179 const MachineFunction *MF = MI.getParent()->getParent();
180 return !AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
189 const MachineFunction *MF = MI.getParent()->getParent();
190 return (AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
197 case R600::KILLGT:
198 case R600::GROUP_BARRIER:
206 return MI.findRegisterUseOperandIdx(R600::AR_X, &RI, false) != -1;
210 return MI.findRegisterDefOperandIdx(R600::AR_X, &RI, false, false) != -1;
219 R600::R600_LDS_SRC_REGRegClass.contains(MO.getReg()))
226 {R600::OpName::src0, R600::OpName::src0_sel},
227 {R600::OpName::src1, R600::OpName::src1_sel},
228 {R600::OpName::src2, R600::OpName::src2_sel},
229 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
230 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
231 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
232 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
233 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
234 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
235 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
236 {R600::OpName::src1_W, R600::OpName::src1_sel_W}
244 return -1;
251 if (MI.getOpcode() == R600::DOT_4) {
253 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
254 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
255 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
256 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
257 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
258 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
259 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
260 {R600::OpName::src1_W, R600::OpName::src1_sel_W},
266 if (Reg == R600::ALU_CONST) {
277 {R600::OpName::src0, R600::OpName::src0_sel},
278 {R600::OpName::src1, R600::OpName::src1_sel},
279 {R600::OpName::src2, R600::OpName::src2_sel},
288 if (Reg == R600::ALU_CONST) {
293 if (Reg == R600::ALU_LITERAL_X) {
295 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal));
312 const std::pair<int, unsigned> DummyPair(-1, 0);
317 Register Reg = Src.first->getReg();
319 if (Reg == R600::OQAP) {
344 Src[1].first = -1;
402 memset(Vector, -1, sizeof(Vector));
410 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) {
437 return IGSrcs.size() - 1;
451 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
452 ResetIdx --;
456 if (ResetIdx == -1)
507 //Todo : support shared src0 - src1 operand
515 unsigned Op = getOperandIdx(MI->getOpcode(), R600::OpName::bank_swizzle);
517 (R600InstrInfo::BankSwizzle)MI->getOperand(Op).getImm());
578 if (!isALUInstr(MI->getOpcode()))
582 if (Src.first->getReg() == R600::ALU_LITERAL_X)
586 if (Src.first->getReg() == R600::ALU_CONST)
588 if (R600::R600_KC0RegClass.contains(Src.first->getReg()) ||
589 R600::R600_KC1RegClass.contains(Src.first->getReg())) {
590 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
591 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
608 case R600::PRED_X:
619 --I;
630 return Opcode == R600::JUMP || Opcode == R600::JUMP_COND;
634 return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 ||
635 Opcode == R600::BRANCH_COND_f32;
650 // R600::BRANCH* instructions are only available after isel and are not
652 if (isBranch(I->getOpcode()))
654 if (!isJump(I->getOpcode())) {
659 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) {
662 I->removeFromParent();
669 if (I == MBB.begin() || !isJump((--I)->getOpcode())) {
670 if (LastOpc == R600::JUMP) {
674 if (LastOpc == R600::JUMP_COND) {
676 while (!isPredicateSetter(predSet->getOpcode())) {
677 predSet = --I;
680 Cond.push_back(predSet->getOperand(1));
681 Cond.push_back(predSet->getOperand(2));
682 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
693 if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) {
694 auto predSet = --I;
695 while (!isPredicateSetter(predSet->getOpcode())) {
696 predSet = --I;
700 Cond.push_back(predSet->getOperand(1));
701 Cond.push_back(predSet->getOperand(2));
702 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
714 if (It->getOpcode() == R600::CF_ALU ||
715 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
732 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
738 PredSet->getOperand(2).setImm(Cond[1].getImm());
740 BuildMI(&MBB, DL, get(R600::JUMP_COND))
742 .addReg(R600::PREDICATE_BIT, RegState::Kill);
746 assert (CfAlu->getOpcode() == R600::CF_ALU);
747 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
753 PredSet->getOperand(2).setImm(Cond[1].getImm());
754 BuildMI(&MBB, DL, get(R600::JUMP_COND))
756 .addReg(R600::PREDICATE_BIT, RegState::Kill);
757 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
761 assert(CfAlu->getOpcode() == R600::CF_ALU);
762 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
778 --I;
779 switch (I->getOpcode()) {
782 case R600::JUMP_COND: {
785 I->eraseFromParent();
789 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
790 CfAlu->setDesc(get(R600::CF_ALU));
793 case R600::JUMP:
794 I->eraseFromParent();
802 --I;
803 switch (I->getOpcode()) {
807 case R600::JUMP_COND: {
810 I->eraseFromParent();
814 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
815 CfAlu->setDesc(get(R600::CF_ALU));
818 case R600::JUMP:
819 I->eraseFromParent();
833 case R600::PRED_SEL_ONE:
834 case R600::PRED_SEL_ZERO:
835 case R600::PREDICATE_BIT:
846 if (MI.getOpcode() == R600::KILLGT)
848 if (MI.getOpcode() == R600::CF_ALU) {
851 if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI))
898 case R600::PRED_SETE_INT:
899 MO.setImm(R600::PRED_SETNE_INT);
901 case R600::PRED_SETNE_INT:
902 MO.setImm(R600::PRED_SETE_INT);
904 case R600::PRED_SETE:
905 MO.setImm(R600::PRED_SETNE);
907 case R600::PRED_SETNE:
908 MO.setImm(R600::PRED_SETE);
916 case R600::PRED_SEL_ZERO:
917 MO2.setReg(R600::PRED_SEL_ONE);
919 case R600::PRED_SEL_ONE:
920 MO2.setReg(R600::PRED_SEL_ZERO);
938 if (MI.getOpcode() == R600::CF_ALU) {
943 if (MI.getOpcode() == R600::DOT_4) {
944 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_X))
946 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Y))
948 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Z))
950 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W))
952 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
953 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
957 if (PIdx != -1) {
960 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
961 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
991 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr);
996 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan);
999 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst);
1004 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1006 getIndirectAddrRegClass()->getRegister(Address));
1013 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val);
1018 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1019 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
1030 MBB->erase(MI);
1033 case R600::R600_EXTRACT_ELT_V2:
1034 case R600::R600_EXTRACT_ELT_V4:
1040 case R600::R600_INSERT_ELT_V2:
1041 case R600::R600_INSERT_ELT_V4:
1058 unsigned StackWidth = TFL->getStackWidth(MF);
1061 if (End == -1)
1066 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1073 return &R600::R600_TReg32_XRegClass;
1091 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1092 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1093 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
1094 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
1096 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg,
1097 R600::AR_X, OffsetReg);
1098 setImmOperand(*MOVA, R600::OpName::write, 0);
1100 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1102 .addReg(R600::AR_X,
1104 setImmOperand(*Mov, R600::OpName::dst_rel, 1);
1123 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1124 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1125 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
1126 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
1128 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg,
1129 R600::AR_X,
1131 setImmOperand(*MOVA, R600::OpName::write, 0);
1132 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1135 .addReg(R600::AR_X,
1137 setImmOperand(*Mov, R600::OpName::src0_rel, 1);
1145 int Offset = -1;
1148 return -1;
1158 if (Reg.isVirtual() || !IndirectRC->contains(Reg))
1163 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
1165 if (IndirectRC->getRegister(RegIndex) == (unsigned)Reg)
1180 return -1;
1184 return -1;
1191 Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg).getFixed();
1221 .addImm(-1); // $src0_sel
1228 .addImm(-1); // $src1_sel
1234 .addReg(R600::PRED_SEL_OFF) // $pred_sel
1255 OPERAND_CASE(R600::OpName::update_exec_mask)
1256 OPERAND_CASE(R600::OpName::update_pred)
1257 OPERAND_CASE(R600::OpName::write)
1258 OPERAND_CASE(R600::OpName::omod)
1259 OPERAND_CASE(R600::OpName::dst_rel)
1260 OPERAND_CASE(R600::OpName::clamp)
1261 OPERAND_CASE(R600::OpName::src0)
1262 OPERAND_CASE(R600::OpName::src0_neg)
1263 OPERAND_CASE(R600::OpName::src0_rel)
1264 OPERAND_CASE(R600::OpName::src0_abs)
1265 OPERAND_CASE(R600::OpName::src0_sel)
1266 OPERAND_CASE(R600::OpName::src1)
1267 OPERAND_CASE(R600::OpName::src1_neg)
1268 OPERAND_CASE(R600::OpName::src1_rel)
1269 OPERAND_CASE(R600::OpName::src1_abs)
1270 OPERAND_CASE(R600::OpName::src1_sel)
1271 OPERAND_CASE(R600::OpName::pred_sel)
1282 assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented");
1285 Opcode = R600::DOT4_r600;
1287 Opcode = R600::DOT4_eg;
1289 MachineOperand &Src0 = MI->getOperand(
1290 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot)));
1291 MachineOperand &Src1 = MI->getOperand(
1292 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot)));
1296 R600::OpName::update_exec_mask,
1297 R600::OpName::update_pred,
1298 R600::OpName::write,
1299 R600::OpName::omod,
1300 R600::OpName::dst_rel,
1301 R600::OpName::clamp,
1302 R600::OpName::src0_neg,
1303 R600::OpName::src0_rel,
1304 R600::OpName::src0_abs,
1305 R600::OpName::src0_sel,
1306 R600::OpName::src1_neg,
1307 R600::OpName::src1_rel,
1308 R600::OpName::src1_abs,
1309 R600::OpName::src1_sel,
1312 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1313 getSlotedOps(R600::OpName::pred_sel, Slot)));
1314 MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel))
1318 MachineOperand &MO = MI->getOperand(
1319 getOperandIdx(MI->getOpcode(), getSlotedOps(Operand, Slot)));
1323 MIB->getOperand(20).setImm(0);
1331 MachineInstr *MovImm = buildDefaultInstruction(BB, I, R600::MOV, DstReg,
1332 R600::ALU_LITERAL_X);
1333 setImmOperand(*MovImm, R600::OpName::literal, Imm);
1340 return buildDefaultInstruction(*MBB, I, R600::MOV, DstReg, SrcReg);
1348 return R600::getNamedOperandIdx(Opcode, Op);
1354 assert(Idx != -1 && "Operand not supported for this instruction.");
1359 //===----------------------------------------------------------------------===//
1361 //===----------------------------------------------------------------------===//
1375 FlagIndex = getOperandIdx(MI, R600::OpName::clamp);
1378 FlagIndex = getOperandIdx(MI, R600::OpName::write);
1382 FlagIndex = getOperandIdx(MI, R600::OpName::last);
1387 FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg);
1390 FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg);
1393 FlagIndex = getOperandIdx(MI, R600::OpName::src2_neg);
1404 FlagIndex = getOperandIdx(MI, R600::OpName::src0_abs);
1407 FlagIndex = getOperandIdx(MI, R600::OpName::src1_abs);
1413 FlagIndex = -1;
1416 assert(FlagIndex != -1 && "Flag not supported for this instruction");