Lines Matching +full:r600 +full:- +full:-
2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefixes=R600 %s
8 ; R600-LABEL: bfi_def:
9 ; R600: ; %bb.0: ; %entry
10 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
11 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
12 ; R600-NEXT: CF_END
13 ; R600-NEXT: PAD
14 ; R600-NEXT: ALU clause starting at 4:
15 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
16 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
17 ; R600-NEXT: BFI_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
19 %0 = xor i32 %x, -1
27 ; SHA-256 Ch function
30 ; R600-LABEL: bfi_sha256_ch:
31 ; R600: ; %bb.0: ; %entry
32 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
33 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
34 ; R600-NEXT: CF_END
35 ; R600-NEXT: PAD
36 ; R600-NEXT: ALU clause starting at 4:
37 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
38 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
39 ; R600-NEXT: BFI_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
48 ; SHA-256 Ma function
51 ; R600-LABEL: bfi_sha256_ma:
52 ; R600: ; %bb.0: ; %entry
53 ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
54 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
55 ; R600-NEXT: CF_END
56 ; R600-NEXT: PAD
57 ; R600-NEXT: ALU clause starting at 4:
58 ; R600-NEXT: XOR_INT * T0.W, KC0[2].Z, KC0[2].W,
59 ; R600-NEXT: BFI_INT * T0.X, PV.W, KC0[3].X, KC0[2].W,
60 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
61 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
72 ; R600-LABEL: v_bitselect_v2i32_pat1:
73 ; R600: ; %bb.0:
74 ; R600-NEXT: CF_END
75 ; R600-NEXT: PAD
83 ; R600-LABEL: v_bitselect_i64_pat_0:
84 ; R600: ; %bb.0:
85 ; R600-NEXT: CF_END
86 ; R600-NEXT: PAD
88 %not.a = xor i64 %a, -1
95 ; R600-LABEL: v_bitselect_i64_pat_1:
96 ; R600: ; %bb.0:
97 ; R600-NEXT: CF_END
98 ; R600-NEXT: PAD
106 ; R600-LABEL: v_bitselect_i64_pat_2:
107 ; R600: ; %bb.0:
108 ; R600-NEXT: CF_END
109 ; R600-NEXT: PAD
117 ; R600-LABEL: v_bfi_sha256_ma_i64:
118 ; R600: ; %bb.0: ; %entry
119 ; R600-NEXT: CF_END
120 ; R600-NEXT: PAD
130 ; R600-LABEL: s_bitselect_i64_pat_0:
131 ; R600: ; %bb.0:
132 ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
133 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
134 ; R600-NEXT: CF_END
135 ; R600-NEXT: PAD
136 ; R600-NEXT: ALU clause starting at 4:
137 ; R600-NEXT: MOV * T0.W, KC0[3].Y,
138 ; R600-NEXT: BFI_INT * T0.W, KC0[2].Y, KC0[2].W, PV.W,
139 ; R600-NEXT: MOV * T1.W, KC0[3].Z,
140 ; R600-NEXT: BFI_INT T1.W, KC0[2].Z, KC0[3].X, PV.W,
141 ; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
142 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
143 ; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
144 ; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
145 ; R600-NEXT: MOV * T1.X, literal.y,
146 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
148 %not.a = xor i64 %a, -1
157 ; R600-LABEL: s_bitselect_i64_pat_1:
158 ; R600: ; %bb.0:
159 ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
160 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
161 ; R600-NEXT: CF_END
162 ; R600-NEXT: PAD
163 ; R600-NEXT: ALU clause starting at 4:
164 ; R600-NEXT: MOV * T0.W, KC0[3].Y,
165 ; R600-NEXT: BFI_INT * T0.W, KC0[2].W, KC0[2].Y, PV.W,
166 ; R600-NEXT: MOV * T1.W, KC0[3].Z,
167 ; R600-NEXT: BFI_INT T1.W, KC0[3].X, KC0[2].Z, PV.W,
168 ; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
169 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
170 ; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
171 ; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
172 ; R600-NEXT: MOV * T1.X, literal.y,
173 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
184 ; R600-LABEL: s_bitselect_i64_pat_2:
185 ; R600: ; %bb.0:
186 ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
187 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
188 ; R600-NEXT: CF_END
189 ; R600-NEXT: PAD
190 ; R600-NEXT: ALU clause starting at 4:
191 ; R600-NEXT: MOV * T0.W, KC0[3].Y,
192 ; R600-NEXT: BFI_INT * T0.W, KC0[2].W, KC0[2].Y, PV.W,
193 ; R600-NEXT: MOV * T1.W, KC0[3].Z,
194 ; R600-NEXT: BFI_INT T1.W, KC0[3].X, KC0[2].Z, PV.W,
195 ; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
196 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
197 ; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
198 ; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
199 ; R600-NEXT: MOV * T1.X, literal.y,
200 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
211 ; R600-LABEL: s_bfi_sha256_ma_i64:
212 ; R600: ; %bb.0: ; %entry
213 ; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
214 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
215 ; R600-NEXT: CF_END
216 ; R600-NEXT: PAD
217 ; R600-NEXT: ALU clause starting at 4:
218 ; R600-NEXT: XOR_INT * T0.W, KC0[2].Y, KC0[2].W,
219 ; R600-NEXT: BFI_INT T0.W, PV.W, KC0[3].Y, KC0[2].W,
220 ; R600-NEXT: XOR_INT * T1.W, KC0[2].Z, KC0[3].X,
221 ; R600-NEXT: BFI_INT T1.W, PS, KC0[3].Z, KC0[3].X,
222 ; R600-NEXT: ADDC_UINT * T2.W, PV.W, literal.x,
223 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
224 ; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
225 ; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
226 ; R600-NEXT: MOV * T1.X, literal.y,
227 ; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)