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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp39 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
40 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
41 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
43 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
44 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
45 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
67 // Tie operands if MI has become a two-address instruction.
68 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
69 if (MI in tieOpsIfNeeded()
77 shortenIIF(MachineInstr & MI,unsigned LLIxL,unsigned LLIxH) shortenIIF() argument
110 shortenOn0(MachineInstr & MI,unsigned Opcode) shortenOn0() argument
120 shortenOn01(MachineInstr & MI,unsigned Opcode) shortenOn01() argument
132 shortenOn001(MachineInstr & MI,unsigned Opcode) shortenOn001() argument
145 shortenOn001AddCC(MachineInstr & MI,unsigned Opcode) shortenOn001AddCC() argument
158 shortenFPConv(MachineInstr & MI,unsigned Opcode) shortenFPConv() argument
180 shortenFusedFPOp(MachineInstr & MI,unsigned Opcode) shortenFusedFPOp() argument
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H A DSystemZInstrInfo.cpp66 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
68 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, in splitMove() argument
70 MachineBasicBlock *MBB = MI->getParent(); in splitMove()
75 MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI); in splitMove()
76 MachineInstr *LowPartMI = &*MI; in splitMove()
102 if (MI->mayStore()) { in splitMove()
107 // If Reg128 was killed, set kill flag on MI. in splitMove()
115 return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) || in splitMove()
116 RI.regsOverlap(Reg, MI->getOperand(3).getReg()); in splitMove()
131 // Split ADJDYNALLOC instruction MI
155 expandRIPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned HighOpcode,bool ConvertHigh) const expandRIPseudo() argument
169 expandRIEPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned LowOpcodeK,unsigned HighOpcode) const expandRIEPseudo() argument
193 expandRXYPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned HighOpcode) const expandRXYPseudo() argument
205 expandLOCPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned HighOpcode) const expandLOCPseudo() argument
215 expandZExtPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned Size) const expandZExtPseudo() argument
290 commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const commuteInstructionImpl() argument
294 __anon6433e3210202(MachineInstr &MI) commuteInstructionImpl() argument
327 isSimpleMove(const MachineInstr & MI,int & FrameIndex,unsigned Flag) isSimpleMove() argument
338 isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const isLoadFromStackSlot() argument
343 isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const isStoreToStackSlot() argument
348 isStackSlotCopy(const MachineInstr & MI,int & DestFrameIndex,int & SrcFrameIndex) const isStackSlotCopy() argument
533 analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int64_t & Mask,int64_t & Value) const analyzeCompare() argument
738 PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Pred) const PredicateInstruction() argument
915 isSimpleBD12Move(const MachineInstr * MI,unsigned Flag) isSimpleBD12Move() argument
968 convertToThreeAddress(MachineInstr & MI,LiveVariables * LV,LiveIntervals * LIS) const convertToThreeAddress() argument
1020 foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,int FrameIndex,LiveIntervals * LIS,VirtRegMap * VRM) const foldMemoryOperandImpl() argument
1349 foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,MachineInstr & LoadMI,LiveIntervals * LIS) const foldMemoryOperandImpl() argument
1923 splitBlockAfter(MachineBasicBlock::iterator MI,MachineBasicBlock * MBB) splitBlockAfter() argument
1932 splitBlockBefore(MachineBasicBlock::iterator MI,MachineBasicBlock * MBB) splitBlockBefore() argument
1990 verifyInstruction(const MachineInstr & MI,StringRef & ErrInfo) const verifyInstruction() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
34 void printInstruction(const MCInst *MI, uint64_t Address,
36 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
38 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
45 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
47 void printOperand(const MCInst *MI, uint64_t Address, unsigned OpNum,
50 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
52 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
55 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
[all …]
H A DARMInstPrinter.cpp88 void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
91 unsigned Opcode = MI->getOpcode(); in printInst()
95 const MCOperand &Reg = MI->getOperand(0); in printInst()
103 const MCOperand &Reg = MI->getOperand(0); in printInst()
111 const MCOperand &Reg = MI->getOperand(0); in printInst()
119 const MCOperand &Reg = MI->getOperand(0); in printInst()
129 const MCOperand &Dst = MI->getOperand(0); in printInst()
130 const MCOperand &MO1 = MI->getOperand(1); in printInst()
131 const MCOperand &MO2 = MI->getOperand(2); in printInst()
132 const MCOperand &MO3 = MI in printInst()
309 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
349 printOperand(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
363 printThumbLdrLabelOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printThumbLdrLabelOperand() argument
394 printSORegRegOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSORegRegOperand() argument
414 printSORegImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSORegImmOperand() argument
431 printAM2PreOrOffsetIndexOp(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printAM2PreOrOffsetIndexOp() argument
462 printAddrModeTBB(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printAddrModeTBB() argument
476 printAddrModeTBH(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printAddrModeTBH() argument
491 printAddrMode2Operand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode2Operand() argument
510 printAddrMode2OffsetOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode2OffsetOperand() argument
536 printAM3PreOrOffsetIndexOp(const MCInst * MI,unsigned Op,raw_ostream & O,bool AlwaysPrintImm0) printAM3PreOrOffsetIndexOp() argument
566 printAddrMode3Operand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode3Operand() argument
581 printAddrMode3OffsetOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode3OffsetOperand() argument
600 printPostIdxImm8Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPostIdxImm8Operand() argument
609 printPostIdxRegOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPostIdxRegOperand() argument
619 printPostIdxImm8s4Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPostIdxImm8s4Operand() argument
629 printMveAddrModeRQOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMveAddrModeRQOperand() argument
647 printLdStmModeOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printLdStmModeOperand() argument
656 printAddrMode5Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode5Operand() argument
682 printAddrMode5FP16Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode5FP16Operand() argument
708 printAddrMode6Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode6Operand() argument
723 printAddrMode7Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode7Operand() argument
733 printAddrMode6OffsetOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrMode6OffsetOperand() argument
746 printBitfieldInvMaskImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printBitfieldInvMaskImmOperand() argument
760 printMemBOption(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMemBOption() argument
767 printInstSyncBOption(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printInstSyncBOption() argument
774 printTraceSyncBOption(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printTraceSyncBOption() argument
781 printShiftImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printShiftImmOperand() argument
796 printPKHLSLShiftImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPKHLSLShiftImm() argument
807 printPKHASRShiftImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPKHASRShiftImm() argument
819 printRegisterList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printRegisterList() argument
839 printGPRPairOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printGPRPairOperand() argument
848 printSetendOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSetendOperand() argument
858 printCPSIMod(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printCPSIMod() argument
864 printCPSIFlag(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printCPSIFlag() argument
876 printMSRMaskOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMSRMaskOperand() argument
958 printBankedRegOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printBankedRegOperand() argument
972 printPredicateOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPredicateOperand() argument
984 printMandatoryRestrictedPredicateOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMandatoryRestrictedPredicateOperand() argument
992 printMandatoryPredicateOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMandatoryPredicateOperand() argument
1000 printMandatoryInvertedPredicateOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMandatoryInvertedPredicateOperand() argument
1008 printSBitModifierOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printSBitModifierOperand() argument
1018 printNoHashImmediate(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printNoHashImmediate() argument
1024 printPImmediate(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPImmediate() argument
1030 printCImmediate(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printCImmediate() argument
1036 printCoprocOptionImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printCoprocOptionImm() argument
1042 printPCLabel(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printPCLabel() argument
1048 printAdrLabelOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAdrLabelOperand() argument
1069 printThumbS4ImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printThumbS4ImmOperand() argument
1076 printThumbSRImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printThumbSRImm() argument
1083 printThumbITMask(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printThumbITMask() argument
1098 printThumbAddrModeRROperand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printThumbAddrModeRROperand() argument
1119 printThumbAddrModeImm5SOperand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O,unsigned Scale) printThumbAddrModeImm5SOperand() argument
1142 printThumbAddrModeImm5S1Operand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printThumbAddrModeImm5S1Operand() argument
1149 printThumbAddrModeImm5S2Operand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printThumbAddrModeImm5S2Operand() argument
1156 printThumbAddrModeImm5S4Operand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printThumbAddrModeImm5S4Operand() argument
1163 printThumbAddrModeSPOperand(const MCInst * MI,unsigned Op,const MCSubtargetInfo & STI,raw_ostream & O) printThumbAddrModeSPOperand() argument
1173 printT2SOOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2SOOperand() argument
1189 printAddrModeImm12Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printAddrModeImm12Operand() argument
1220 printT2AddrModeImm8Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeImm8Operand() argument
1247 printT2AddrModeImm8s4Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeImm8s4Operand() argument
1282 printT2AddrModeImm0_1020s4Operand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeImm0_1020s4Operand() argument
1298 printT2AddrModeImm8OffsetOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeImm8OffsetOperand() argument
1313 printT2AddrModeImm8s4OffsetOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeImm8s4OffsetOperand() argument
1330 printT2AddrModeSoRegOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printT2AddrModeSoRegOperand() argument
1355 printFPImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printFPImmOperand() argument
1362 printVMOVModImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVMOVModImmOperand() argument
1374 printImmPlusOneOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printImmPlusOneOperand() argument
1381 printRotImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printRotImmOperand() argument
1392 printModImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printModImmOperand() argument
1434 printFBits16(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printFBits16() argument
1439 printFBits32(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printFBits32() argument
1444 printVectorIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorIndex() argument
1450 printVectorListOne(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListOne() argument
1458 printVectorListTwo(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListTwo() argument
1471 printVectorListTwoSpaced(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListTwoSpaced() argument
1484 printVectorListThree(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListThree() argument
1499 printVectorListFour(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListFour() argument
1516 printVectorListOneAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListOneAllLanes() argument
1525 printVectorListTwoAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListTwoAllLanes() argument
1539 printVectorListThreeAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListThreeAllLanes() argument
1555 printVectorListFourAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListFourAllLanes() argument
1574 printVectorListTwoSpacedAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListTwoSpacedAllLanes() argument
1587 printVectorListThreeSpacedAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListThreeSpacedAllLanes() argument
1602 printVectorListFourSpacedAllLanes(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListFourSpacedAllLanes() argument
1618 printVectorListThreeSpaced(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListThreeSpaced() argument
1634 printVectorListFourSpaced(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVectorListFourSpaced() argument
1652 printMVEVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMVEVectorList() argument
1666 printComplexRotationOp(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printComplexRotationOp() argument
1673 printVPTPredicateOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVPTPredicateOperand() argument
1681 printVPTMask(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printVPTMask() argument
1697 printMveSaturateOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printMveSaturateOp() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp239 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, in getVectorRegSize()
241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getVectorRegSize()
250 static void printMasking(raw_ostream &OS, const MCInst *MI, in getRegOperandNumElts()
252 const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); in getRegOperandNumElts()
264 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
274 static bool printFMAComments(const MCInst *MI, raw_ostream &OS, in printMasking()
277 unsigned NumOperands = MI->getNumOperands(); in printMasking()
296 switch (MI->getOpcode()) { in printFMAComments()
302 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
306 Mul2Name = getRegName(MI in printFMAComments()
249 getRegOperandNumElts(const MCInst * MI,unsigned ScalarSize,unsigned OperandIndex) getRegOperandNumElts() argument
260 printMasking(raw_ostream & OS,const MCInst * MI,const MCInstrInfo & MCII) printMasking() argument
284 printFMAComments(const MCInst * MI,raw_ostream & OS,const MCInstrInfo & MCII) printFMAComments() argument
638 EmitAnyX86InstComments(const MCInst * MI,raw_ostream & OS,const MCInstrInfo & MCII) EmitAnyX86InstComments() argument
[all...]
H A DX86ATTInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
39 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
40 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
44 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
[all …]
H A DX86IntelInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
40 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
41 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
45 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
46 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h27 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
28 void printInstruction(const MCInst *MI, uint64_t Address,
33 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
39 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
41 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
43 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
48 void printNamedBit(const MCInst *MI, unsigne
103 printOperand(const MCInst * MI,uint64_t,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h87 /// Replace \p MI by a sequence of legal instructions that can implement the
88 /// same operation. Note that this means \p MI may be deleted, so any iterator
90 /// be initialized to the MachineFunction containing \p MI.
93 /// registers as \p MI.
94 LegalizeResult legalizeInstrStep(MachineInstr &MI,
98 LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
102 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
107 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
110 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
114 LegalizeResult lower(MachineInstr &MI, unsigne
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H A DCombinerHelper.h52 MachineInstr *MI; member
170 /// If \p MI is COPY, try to combine it.
171 /// Returns true if MI changed.
172 bool tryCombineCopy(MachineInstr &MI);
173 bool matchCombineCopy(MachineInstr &MI);
174 void applyCombineCopy(MachineInstr &MI);
188 /// If \p MI is extend that consumes the result of a load, try to combine it.
189 /// Returns true if MI changed.
190 bool tryCombineExtendingLoads(MachineInstr &MI);
191 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTupl
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
38 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
41 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
45 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
48 void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O);
49 void printImmediate(const MCInst *MI, unsigned opNum, raw_ostream &O);
51 void printMoveMask(const MCInst *MI, unsigned opNum, raw_ostream &O);
53 void printMoveMaskR(const MCInst *MI, unsigned opNum, raw_ostream &O);
54 void printDisp(const MCInst *MI, unsigned opNum, raw_ostream &O);
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp76 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction()
77 CurrCycleInstr = MI; in EmitInstruction()
123 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { in isXDL()
124 unsigned Opcode = MI.getOpcode(); in isXDL()
126 if (!SIInstrInfo::isMAI(MI) || in isXDL()
139 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS()
140 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
143 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
154 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
155 int GDS = AMDGPU::getNamedOperandIdx(MI in isSendMsgTraceDataOrGDS()
75 EmitInstruction(MachineInstr * MI) EmitInstruction() argument
122 isXDL(const GCNSubtarget & ST,const MachineInstr & MI) isXDL() argument
138 isSendMsgTraceDataOrGDS(const SIInstrInfo & TII,const MachineInstr & MI) isSendMsgTraceDataOrGDS() argument
163 isPermlane(const MachineInstr & MI) isPermlane() argument
172 isLdsDma(const MachineInstr & MI) isLdsDma() argument
185 MachineInstr *MI = SU->getInstr(); getHazardType() local
262 insertNoopsInBundle(MachineInstr * MI,const SIInstrInfo & TII,unsigned Quantity) insertNoopsInBundle() argument
281 MachineBasicBlock::instr_iterator MI = std::next(CurrCycleInstr->getIterator()); processBundle() local
306 runOnInstruction(MachineInstr * MI) runOnInstruction() argument
320 PreEmitNoops(MachineInstr * MI) PreEmitNoops() argument
329 PreEmitNoopsCommon(MachineInstr * MI) PreEmitNoopsCommon() argument
535 getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard,const MachineInstr * MI,IsExpiredFn IsExpired) getWaitStatesSince() argument
572 __anon7fc9b90f0402(const MachineInstr &MI) getWaitStatesSinceDef() argument
581 __anon7fc9b90f0502(const MachineInstr &MI) getWaitStatesSinceSetReg() argument
607 addClauseInst(const MachineInstr & MI) addClauseInst() argument
611 breaksSMEMSoftClause(MachineInstr * MI) breaksSMEMSoftClause() argument
615 breaksVMEMSoftClause(MachineInstr * MI) breaksVMEMSoftClause() argument
679 __anon7fc9b90f0602(const MachineInstr &MI) checkSMRDHazards() argument
682 __anon7fc9b90f0702(const MachineInstr &MI) checkSMRDHazards() argument
724 __anon7fc9b90f0802(const MachineInstr &MI) checkVMEMHazards() argument
747 __anon7fc9b90f0902(const MachineInstr &MI) checkDPPHazards() argument
776 __anon7fc9b90f0b02(const MachineInstr &MI) checkDivFMasHazards() argument
790 __anon7fc9b90f0c02(const MachineInstr &MI) checkGetRegHazards() argument
803 __anon7fc9b90f0d02(const MachineInstr &MI) checkSetRegHazards() argument
810 createsVALUHazard(const MachineInstr & MI) createsVALUHazard() argument
872 __anon7fc9b90f0e02(const MachineInstr &MI) checkVALUHazardsHelper() argument
890 __anon7fc9b90f0f02(const MachineInstr &MI) checkVALUHazards() argument
914 __anon7fc9b90f1002(const MachineInstr &MI) checkVALUHazards() argument
956 __anon7fc9b90f1102(const MachineInstr &MI) checkVALUHazards() argument
1060 __anon7fc9b90f1202(const MachineInstr &MI) checkRWLaneHazards() argument
1076 __anon7fc9b90f1302(const MachineInstr &MI) checkRFEHazards() argument
1083 checkReadM0Hazards(MachineInstr * MI) checkReadM0Hazards() argument
1086 __anon7fc9b90f1402(const MachineInstr &MI) checkReadM0Hazards() argument
1091 fixHazards(MachineInstr * MI) fixHazards() argument
1108 fixVcmpxPermlaneHazards(MachineInstr * MI) fixVcmpxPermlaneHazards() argument
1114 __anon7fc9b90f1502(const MachineInstr &MI) fixVcmpxPermlaneHazards() argument
1120 __anon7fc9b90f1602(const MachineInstr &MI, int) fixVcmpxPermlaneHazards() argument
1144 fixVMEMtoScalarWriteHazards(MachineInstr * MI) fixVMEMtoScalarWriteHazards() argument
1172 __anon7fc9b90f1802(const MachineInstr &MI, int) fixVMEMtoScalarWriteHazards() argument
1191 fixSMEMtoVectorWriteHazards(MachineInstr * MI) fixSMEMtoVectorWriteHazards() argument
1231 __anon7fc9b90f1a02(const MachineInstr &MI, int) fixSMEMtoVectorWriteHazards() argument
1278 fixVcmpxExecWARHazard(MachineInstr * MI) fixVcmpxExecWARHazard() argument
1297 __anon7fc9b90f1c02(const MachineInstr &MI, int) fixVcmpxExecWARHazard() argument
1331 for (auto &MI : MBB) { shouldRunLdsBranchVmemWARHazardFixup() local
1348 fixLdsBranchVmemWARHazard(MachineInstr * MI) fixLdsBranchVmemWARHazard() argument
1355 __anon7fc9b90f1d02(const MachineInstr &MI) fixLdsBranchVmemWARHazard() argument
1405 fixLdsDirectVALUHazard(MachineInstr * MI) fixLdsDirectVALUHazard() argument
1428 __anon7fc9b90f2402(const MachineInstr &MI) fixLdsDirectVALUHazard() argument
1449 fixLdsDirectVMEMHazard(MachineInstr * MI) fixLdsDirectVMEMHazard() argument
1489 fixVALUPartialForwardingHazard(MachineInstr * MI) fixVALUPartialForwardingHazard() argument
1621 __anon7fc9b90f2802(StateType &State, const MachineInstr &MI) fixVALUPartialForwardingHazard() argument
1638 fixVALUTransUseHazard(MachineInstr * MI) fixVALUTransUseHazard() argument
1697 __anon7fc9b90f2a02(StateType &State, const MachineInstr &MI) fixVALUTransUseHazard() argument
1718 fixWMMAHazards(MachineInstr * MI) fixWMMAHazards() argument
1792 fixShift64HighRegBug(MachineInstr * MI) fixShift64HighRegBug() argument
1895 checkNSAtoVMEMHazard(MachineInstr * MI) checkNSAtoVMEMHazard() argument
1920 checkFPAtomicToDenormModeHazard(MachineInstr * MI) checkFPAtomicToDenormModeHazard() argument
1936 __anon7fc9b90f2f02(const MachineInstr &MI, int WaitStates) checkFPAtomicToDenormModeHazard() argument
1959 checkMAIHazards(MachineInstr * MI) checkMAIHazards() argument
1965 checkMFMAPadding(MachineInstr * MI) checkMFMAPadding() argument
1976 __anon7fc9b90f3002(const MachineInstr &MI) checkMFMAPadding() argument
1995 checkMAIHazards908(MachineInstr * MI) checkMAIHazards908() argument
1999 __anon7fc9b90f3102(const MachineInstr &MI) checkMAIHazards908() argument
2049 __anon7fc9b90f3202(const MachineInstr &MI) checkMAIHazards908() argument
2095 __anon7fc9b90f3302(const MachineInstr &MI) checkMAIHazards908() argument
2128 __anon7fc9b90f3402(const MachineInstr &MI) checkMAIHazards908() argument
2159 checkMAIHazards90A(MachineInstr * MI) checkMAIHazards90A() argument
2163 __anon7fc9b90f3502(const MachineInstr &MI) checkMAIHazards90A() argument
2167 __anon7fc9b90f3602(const MachineInstr &MI) checkMAIHazards90A() argument
2225 __anon7fc9b90f3702(const MachineInstr &MI) checkMAIHazards90A() argument
2369 checkMAILdStHazards(MachineInstr * MI) checkMAILdStHazards() argument
2376 __anon7fc9b90f3802(const MachineInstr &MI) checkMAILdStHazards() argument
2397 __anon7fc9b90f3902(const MachineInstr &MI) checkMAILdStHazards() argument
2401 __anon7fc9b90f3a02(const MachineInstr &MI) checkMAILdStHazards() argument
2416 checkMAIVALUHazards(MachineInstr * MI) checkMAIVALUHazards() argument
2420 __anon7fc9b90f3b02(const MachineInstr &MI) checkMAIVALUHazards() argument
2440 __anon7fc9b90f3c02(const MachineInstr &MI) checkMAIVALUHazards() argument
2449 __anon7fc9b90f3d02(const MachineInstr &MI) checkMAIVALUHazards() argument
2458 __anon7fc9b90f3e02(const MachineInstr &MI) checkMAIVALUHazards() argument
2681 __anon7fc9b90f3f02(const MachineInstr &MI) checkMAIVALUHazards() argument
2733 __anon7fc9b90f4002(const MachineInstr &MI) ShouldPreferAnother() argument
2740 MachineInstr *MI = SU->getInstr(); ShouldPreferAnother() local
2750 fixVALUMaskWriteHazard(MachineInstr * MI) fixVALUMaskWriteHazard() argument
[all...]
H A DSIInstrInfo.h52 void insert(MachineInstr *MI);
71 bool isDeferred(MachineInstr *MI);
107 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
114 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
179 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
186 isCopyInstrImpl(const MachineInstr &MI) const override;
188 bool swapSourceModifiers(MachineInstr &MI,
192 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
234 bool isSafeToSink(MachineInstr &MI, MachineBasicBloc
318 commuteOpcode(const MachineInstr & MI) commuteOpcode() argument
408 isSALU(const MachineInstr & MI) isSALU() argument
416 isVALU(const MachineInstr & MI) isVALU() argument
424 isImage(const MachineInstr & MI) isImage() argument
432 isVMEM(const MachineInstr & MI) isVMEM() argument
440 isSOP1(const MachineInstr & MI) isSOP1() argument
448 isSOP2(const MachineInstr & MI) isSOP2() argument
456 isSOPC(const MachineInstr & MI) isSOPC() argument
464 isSOPK(const MachineInstr & MI) isSOPK() argument
472 isSOPP(const MachineInstr & MI) isSOPP() argument
480 isPacked(const MachineInstr & MI) isPacked() argument
488 isVOP1(const MachineInstr & MI) isVOP1() argument
496 isVOP2(const MachineInstr & MI) isVOP2() argument
504 isVOP3(const MachineInstr & MI) isVOP3() argument
512 isSDWA(const MachineInstr & MI) isSDWA() argument
520 isVOPC(const MachineInstr & MI) isVOPC() argument
528 isMUBUF(const MachineInstr & MI) isMUBUF() argument
536 isMTBUF(const MachineInstr & MI) isMTBUF() argument
544 isSMRD(const MachineInstr & MI) isSMRD() argument
554 isDS(const MachineInstr & MI) isDS() argument
562 isLDSDMA(const MachineInstr & MI) isLDSDMA() argument
570 isGWS(const MachineInstr & MI) isGWS() argument
580 isMIMG(const MachineInstr & MI) isMIMG() argument
588 isVIMAGE(const MachineInstr & MI) isVIMAGE() argument
596 isVSAMPLE(const MachineInstr & MI) isVSAMPLE() argument
604 isGather4(const MachineInstr & MI) isGather4() argument
612 isFLAT(const MachineInstr & MI) isFLAT() argument
618 isSegmentSpecificFLAT(const MachineInstr & MI) isSegmentSpecificFLAT() argument
628 isFLATGlobal(const MachineInstr & MI) isFLATGlobal() argument
636 isFLATScratch(const MachineInstr & MI) isFLATScratch() argument
649 isEXP(const MachineInstr & MI) isEXP() argument
653 isDualSourceBlendEXP(const MachineInstr & MI) isDualSourceBlendEXP() argument
665 isAtomicNoRet(const MachineInstr & MI) isAtomicNoRet() argument
673 isAtomicRet(const MachineInstr & MI) isAtomicRet() argument
681 isAtomic(const MachineInstr & MI) isAtomic() argument
691 mayWriteLDSThroughDMA(const MachineInstr & MI) mayWriteLDSThroughDMA() argument
695 isWQM(const MachineInstr & MI) isWQM() argument
703 isDisableWQM(const MachineInstr & MI) isDisableWQM() argument
711 isVGPRSpill(const MachineInstr & MI) isVGPRSpill() argument
719 isSGPRSpill(const MachineInstr & MI) isSGPRSpill() argument
744 isDPP(const MachineInstr & MI) isDPP() argument
752 isTRANS(const MachineInstr & MI) isTRANS() argument
760 isVOP3P(const MachineInstr & MI) isVOP3P() argument
768 isVINTRP(const MachineInstr & MI) isVINTRP() argument
776 isMAI(const MachineInstr & MI) isMAI() argument
784 isMFMA(const MachineInstr & MI) isMFMA() argument
789 isDOT(const MachineInstr & MI) isDOT() argument
793 isWMMA(const MachineInstr & MI) isWMMA() argument
801 isMFMAorWMMA(const MachineInstr & MI) isMFMAorWMMA() argument
805 isSWMMAC(const MachineInstr & MI) isSWMMAC() argument
817 isLDSDIR(const MachineInstr & MI) isLDSDIR() argument
825 isVINTERP(const MachineInstr & MI) isVINTERP() argument
833 isScalarUnit(const MachineInstr & MI) isScalarUnit() argument
837 usesVM_CNT(const MachineInstr & MI) usesVM_CNT() argument
841 usesLGKM_CNT(const MachineInstr & MI) usesLGKM_CNT() argument
845 sopkIsZext(const MachineInstr & MI) sopkIsZext() argument
855 isScalarStore(const MachineInstr & MI) isScalarStore() argument
863 isFixedSize(const MachineInstr & MI) isFixedSize() argument
871 hasFPClamp(const MachineInstr & MI) hasFPClamp() argument
879 hasIntClamp(const MachineInstr & MI) hasIntClamp() argument
883 getClampMask(const MachineInstr & MI) getClampMask() argument
891 usesFPDPRounding(const MachineInstr & MI) usesFPDPRounding() argument
899 isFPAtomic(const MachineInstr & MI) isFPAtomic() argument
907 isNeverUniform(const MachineInstr & MI) isNeverUniform() argument
922 doesNotReadTiedSource(const MachineInstr & MI) doesNotReadTiedSource() argument
951 isVGPRCopy(const MachineInstr & MI) isVGPRCopy() argument
959 hasVGPRUses(const MachineInstr & MI) hasVGPRUses() argument
999 isInlineConstant(const MachineInstr & MI,const MachineOperand & UseMO,const MachineOperand & DefMO) isInlineConstant() argument
1012 isInlineConstant(const MachineInstr & MI,unsigned OpIdx) isInlineConstant() argument
1017 isInlineConstant(const MachineInstr & MI,unsigned OpIdx,const MachineOperand & MO) isInlineConstant() argument
1102 getOpSize(const MachineInstr & MI,unsigned OpNo) getOpSize() argument
1201 getNamedOperand(const MachineInstr & MI,unsigned OpName) getNamedOperand() argument
1207 getNamedImmOperand(const MachineInstr & MI,unsigned OpName) getNamedImmOperand() argument
[all...]
H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInf
[all...]
H A DSIMemoryLegalizer.cpp222 /// Reports unsupported message \p Msg for \p MI to LLVM context.
223 void reportUnsupported(const MachineBasicBlock::iterator &MI,
236 /// \returns Info constructed from \p MI, which has at least machine memory
239 constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
246 /// \returns Load info if \p MI is a load operation, "std::nullopt" otherwise.
248 getLoadInfo(const MachineBasicBlock::iterator &MI) const;
250 /// \returns Store info if \p MI is a store operation, "std::nullopt"
253 getStoreInfo(const MachineBasicBlock::iterator &MI) const;
255 /// \returns Atomic fence info if \p MI is an atomic fence operation,
258 getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) cons
663 reportUnsupported(const MachineBasicBlock::iterator & MI,const char * Msg) const reportUnsupported() argument
864 enableNamedBit(const MachineBasicBlock::iterator MI,AMDGPU::CPol::CPol Bit) const enableNamedBit() argument
893 enableLoadCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableLoadCacheBypass() argument
928 enableStoreCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableStoreCacheBypass() argument
941 enableRMWCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableRMWCacheBypass() argument
956 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
1000 insertWait(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsCrossAddrSpaceOrdering,Position Pos) const insertWait() argument
1098 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
1143 insertRelease(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,bool IsCrossAddrSpaceOrdering,Position Pos) const insertRelease() argument
1152 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
1204 enableLoadCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableLoadCacheBypass() argument
1246 enableStoreCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableStoreCacheBypass() argument
1281 enableRMWCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableRMWCacheBypass() argument
1309 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
1353 insertWait(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsCrossAddrSpaceOrdering,Position Pos) const insertWait() argument
1381 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
1447 insertRelease(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,bool IsCrossAddrSpaceOrdering,Position Pos) const insertRelease() argument
1498 enableLoadCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableLoadCacheBypass() argument
1542 enableStoreCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableStoreCacheBypass() argument
1582 enableRMWCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableRMWCacheBypass() argument
1611 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
1650 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
1736 insertRelease(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,bool IsCrossAddrSpaceOrdering,Position Pos) const insertRelease() argument
1800 enableLoadCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableLoadCacheBypass() argument
1843 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
1893 insertWait(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsCrossAddrSpaceOrdering,Position Pos) const insertWait() argument
2014 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
2070 enableLoadCacheBypass(const MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace) const enableLoadCacheBypass() argument
2111 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
2164 setTH(const MachineBasicBlock::iterator MI,AMDGPU::CPol::CPol Value) const setTH() argument
2179 setScope(const MachineBasicBlock::iterator MI,AMDGPU::CPol::CPol Value) const setScope() argument
2194 insertWait(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsCrossAddrSpaceOrdering,Position Pos) const insertWait() argument
2290 insertAcquire(MachineBasicBlock::iterator & MI,SIAtomicScope Scope,SIAtomicAddrSpace AddrSpace,Position Pos) const insertAcquire() argument
2347 enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator & MI,SIAtomicAddrSpace AddrSpace,SIMemOp Op,bool IsVolatile,bool IsNonTemporal) const enableVolatileAndOrNonTemporal() argument
2385 for (auto &MI : AtomicPseudoMIs) removeAtomicPseudoMIs() local
2393 expandLoad(const SIMemOpInfo & MOI,MachineBasicBlock::iterator & MI) expandLoad() argument
2438 expandStore(const SIMemOpInfo & MOI,MachineBasicBlock::iterator & MI) expandStore() argument
2471 expandAtomicFence(const SIMemOpInfo & MOI,MachineBasicBlock::iterator & MI) expandAtomicFence() argument
2518 expandAtomicCmpxchgOrRmw(const SIMemOpInfo & MOI,MachineBasicBlock::iterator & MI) expandAtomicCmpxchgOrRmw() argument
2571 for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) { runOnMachineFunction() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h30 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
36 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
37 virtual void printInstruction(const MCInst *MI, uint64_t Address,
39 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
41 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
52 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI,
56 bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
59 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h58 static inline bool isVCTP(const MachineInstr *MI) { in isVCTP() argument
59 switch (MI->getOpcode()) { in isVCTP()
71 static inline bool isDoLoopStart(const MachineInstr &MI) { in isDoLoopStart() argument
72 return MI.getOpcode() == ARM::t2DoLoopStart || in isDoLoopStart()
73 MI.getOpcode() == ARM::t2DoLoopStartTP; in isDoLoopStart()
76 static inline bool isWhileLoopStart(const MachineInstr &MI) { in isWhileLoopStart() argument
77 return MI.getOpcode() == ARM::t2WhileLoopStart || in isWhileLoopStart()
78 MI.getOpcode() == ARM::t2WhileLoopStartLR || in isWhileLoopStart()
79 MI.getOpcode() == ARM::t2WhileLoopStartTP; in isWhileLoopStart()
82 static inline bool isLoopStart(const MachineInstr &MI) { in isLoopStart() argument
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp39 void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
42 if (!printAliasInstr(MI, Address, STI, OS)) in printInst()
43 printInstruction(MI, Address, STI, OS); in printInst()
47 void VEInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
49 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
67 void VEInstPrinter::printMemASXOperand(const MCInst *MI, int OpNum, in printMemASXOperand() argument
72 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
74 printOperand(MI, OpNum + 1, STI, O); in printMemASXOperand()
78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp77 void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
80 printInstruction(MI, Address, O); in printInst()
85 void SystemZInstPrinter::printUImmOperand(const MCInst *MI, int OpNum, in printUImmOperand() argument
87 const MCOperand &MO = MI->getOperand(OpNum); in printUImmOperand()
98 void SystemZInstPrinter::printSImmOperand(const MCInst *MI, int OpNum, in printSImmOperand() argument
100 const MCOperand &MO = MI->getOperand(OpNum); in printSImmOperand()
105 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
110 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, in printU1ImmOperand() argument
112 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
115 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, in printU2ImmOperand() argument
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
42 printOperand(MI, OpNo0, OS); in printInst()
44 printOperand(MI, OpNo1, OS); in printInst()
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset() argument
49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm() argument
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
57 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); in isPreIncrementForm()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp30 unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx, in getOImmOpValue() argument
33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
39 CSKYMCCodeEmitter::getImmOpValueIDLY(const MCInst &MI, unsigned Idx, in getImmOpValueIDLY() argument
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
50 CSKYMCCodeEmitter::getImmOpValueMSBSize(const MCInst &MI, unsigned Idx, in getImmOpValueMSBSize() argument
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
54 const MCOperand &LSB = MI.getOperand(Idx + 1); in getImmOpValueMSBSize()
68 void CSKYMCCodeEmitter::expandJBTF(const MCInst &MI, SmallVectorImpl<char> &CB, in expandJBTF() argument
77 MCInstBuilder(MI.getOpcode() == CSKY::JBT_E ? CSKY::BF16 : CSKY::BT16) in expandJBTF()
78 .addOperand(MI.getOperand(0)) in expandJBTF()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp70 void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
73 printInstruction(MI, Address, O); in printInst()
81 void XtensaInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
83 printOperand(MI->getOperand(OpNum), O); in printOperand()
86 void XtensaInstPrinter::printMemOperand(const MCInst *MI, int OpNum, in printMemOperand() argument
88 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
90 printOperand(MI, OpNum + 1, OS); in printMemOperand()
93 void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum, in printBranchTarget() argument
95 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
80 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
83 switch (MI->getOpcode()) { in printInst()
93 printSaveRestore(MI, STI, O); in printInst()
98 printSaveRestore(MI, STI, O); in printInst()
103 printSaveRestore(MI, STI, O); in printInst()
108 printSaveRestore(MI, STI, O); in printInst()
114 if (!printAliasInstr(MI, Address, STI, O) && in printInst()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
202 /// into real instructions. The target can edit MI in place, or it can insert
203 /// new instructions and erase MI. The function should return true if
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
221 MachineBasicBlock::iterator MI) const override;
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) cons
514 changeAddrMode_abs_io(const MachineInstr & MI) changeAddrMode_abs_io() argument
517 changeAddrMode_io_abs(const MachineInstr & MI) changeAddrMode_io_abs() argument
520 changeAddrMode_io_rr(const MachineInstr & MI) changeAddrMode_io_rr() argument
523 changeAddrMode_rr_io(const MachineInstr & MI) changeAddrMode_rr_io() argument
526 changeAddrMode_rr_ur(const MachineInstr & MI) changeAddrMode_rr_ur() argument
529 changeAddrMode_ur_rr(const MachineInstr & MI) changeAddrMode_ur_rr() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp50 for (MachineInstr &MI : MBB) { in addConstantsToTrack()
51 if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant)) in addConstantsToTrack()
53 ToErase.push_back(&MI); in addConstantsToTrack()
54 Register SrcReg = MI.getOperand(2).getReg(); in addConstantsToTrack()
57 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
64 RegsAlreadyAddedToDT[&MI] = Reg; in addConstantsToTrack()
101 RegsAlreadyAddedToDT[&MI] = Reg; in foldConstantsIntoIntrinsics()
102 // This MI is unused and will be removed. If the MI uses in foldConstantsIntoIntrinsics()
104 assert(MI in foldConstantsIntoIntrinsics()
168 propagateSPIRVType(MachineInstr * MI,SPIRVGlobalRegistry * GR,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) propagateSPIRVType() argument
263 MachineInstr &MI = *MII; generateAssignInstrs() local
369 processInstr(MachineInstr & MI,MachineIRBuilder & MIB,MachineRegisterInfo & MRI,SPIRVGlobalRegistry * GR) processInstr() argument
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