Lines Matching full:mi
50 for (MachineInstr &MI : MBB) {
51 if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant))
53 ToErase.push_back(&MI);
54 Register SrcReg = MI.getOperand(2).getReg();
57 MI.getOperand(3).getMetadata()->getOperand(0))
64 RegsAlreadyAddedToDT[&MI] = Reg;
101 RegsAlreadyAddedToDT[&MI] = Reg;
102 // This MI is unused and will be removed. If the MI uses
104 assert(MI.getOperand(2).isReg() && "Reg operand is expected");
105 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg());
112 for (MachineInstr *MI : ToErase) {
113 Register Reg = MI->getOperand(2).getReg();
114 if (RegsAlreadyAddedToDT.contains(MI))
115 Reg = RegsAlreadyAddedToDT[MI];
116 auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg());
119 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg);
120 MI->eraseFromParent();
122 for (MachineInstr *MI : ToEraseComposites)
123 MI->eraseFromParent();
133 for (MachineInstr &MI : MBB) {
134 if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name))
136 unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift;
137 while (MI.getOperand(NumOp).isReg()) {
138 MachineOperand &MOp = MI.getOperand(NumOp);
141 MI.removeOperand(NumOp);
142 MI.addOperand(MachineOperand::CreateImm(
150 for (MachineInstr *MI : ToErase)
151 MI->eraseFromParent();
175 for (MachineInstr &MI : MBB) {
176 if (!isSpvIntrinsic(MI, Intrinsic::spv_bitcast) &&
177 !isSpvIntrinsic(MI, Intrinsic::spv_ptrcast))
179 assert(MI.getOperand(2).isReg());
180 MIB.setInsertPt(*MI.getParent(), MI);
181 ToErase.push_back(&MI);
182 if (isSpvIntrinsic(MI, Intrinsic::spv_bitcast)) {
183 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
186 Register Def = MI.getOperand(0).getReg();
187 Register Source = MI.getOperand(2).getReg();
188 Type *ElemTy = getMDOperandAsType(MI.getOperand(3).getMetadata(), 0);
191 BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
192 addressSpaceToStorageClass(MI.getOperand(4).getImm(), *ST));
207 for (MachineInstr *MI : ToErase)
208 MI->eraseFromParent();
225 static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
229 assert(MI && "Machine instr is expected");
230 if (MI->getOperand(0).isReg()) {
231 Register Reg = MI->getOperand(0).getReg();
234 switch (MI->getOpcode()) {
236 MIB.setInsertPt(*MI->getParent(), MI);
237 Type *Ty = MI->getOperand(1).getCImm()->getType();
242 MIB.setInsertPt(*MI->getParent(), MI);
243 const GlobalValue *Global = MI->getOperand(1).getGlobal();
253 if (MI->getOperand(1).isReg()) {
255 MRI.getVRegDef(MI->getOperand(1).getReg())) {
278 MachineOperand &Op = MI->getOperand(1);
389 // when processing the actual MI (i.e. not pseudo one).
403 void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
405 assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg()));
407 *(MRI.use_instr_begin(MI.getOperand(0).getReg()));
409 createNewIdReg(nullptr, MI.getOperand(0).getReg(), MRI, *GR).first;
411 MI.getOperand(0).setReg(NewReg);
412 MIB.setInsertPt(*MI.getParent(),
413 (MI.getNextNode() ? MI.getNextNode()->getIterator()
414 : MI.getParent()->end()));
415 for (auto &Op : MI.operands()) {
444 MachineInstr &MI = *MII;
445 unsigned MIOp = MI.getOpcode();
448 for (const auto &MOP : MI.operands())
452 if (isSpvIntrinsic(MI, Intrinsic::spv_assign_ptr_type)) {
453 Register Reg = MI.getOperand(1).getReg();
454 MIB.setInsertPt(*MI.getParent(), MI.getIterator());
455 Type *ElementTy = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
458 BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
459 addressSpaceToStorageClass(MI.getOperand(3).getImm(), *ST));
467 ToErase.push_back(&MI);
468 } else if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
469 Register Reg = MI.getOperand(1).getReg();
470 Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
477 ToErase.push_back(&MI);
486 Register Reg = MI.getOperand(0).getReg();
496 auto TargetExtIt = TargetExtConstTypes.find(&MI);
498 ? MI.getOperand(1).getCImm()->getType()
500 const ConstantInt *OpCI = MI.getOperand(1).getCImm();
509 RegsAlreadyAddedToDT[&MI] = PrimaryReg;
510 ToErase.push_back(&MI);
515 Ty = MI.getOperand(1).getFPImm()->getType();
519 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
529 MI.getNumExplicitOperands() - MI.getNumExplicitDefs();
535 propagateSPIRVType(&MI, GR, MRI, MIB);
544 for (MachineInstr *MI : ToErase) {
545 auto It = RegsAlreadyAddedToDT.find(MI);
546 if (RegsAlreadyAddedToDT.contains(MI))
547 MRI.replaceRegWith(MI->getOperand(0).getReg(), It->second);
548 MI->eraseFromParent();
554 for (MachineInstr &MI : MBB) {
555 switch (MI.getOpcode()) {
563 propagateSPIRVType(&MI, GR, MRI, MIB);
578 for (MachineInstr &MI : MBB) {
579 if (isTypeFoldingSupported(MI.getOpcode()))
580 processInstr(MI, MIB, MRI, GR);
585 for (MachineInstr &MI : MBB) {
589 if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
591 Register SrcReg = MI.getOperand(1).getReg();
595 Register DstReg = MI.getOperand(0).getReg();
709 for (MachineInstr *MI : ToProcess)
710 MI->eraseFromParent();
718 for (MachineInstr &MI : MBB) {
719 if (isSpvIntrinsic(MI, Intrinsic::spv_inline_asm) ||
720 MI.getOpcode() == TargetOpcode::INLINEASM)
721 ToProcess.push_back(&MI);
738 for (MachineInstr &MI : MBB) {
739 if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_decoration))
741 MIB.setInsertPt(*MI.getParent(), MI);
742 buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
743 MI.getOperand(2).getMetadata());
744 ToErase.push_back(&MI);
747 for (MachineInstr *MI : ToErase)
748 MI->eraseFromParent();
761 for (MachineInstr &MI : MBB) {
762 if (!isSpvIntrinsic(MI, Intrinsic::spv_switch))
766 for (unsigned i = 2; i < MI.getNumOperands(); ++i) {
767 Register Reg = MI.getOperand(i).getReg();
780 Switches.push_back(std::make_pair(&MI, NewOps));
786 MachineInstr &MI = *SwIt.first;
798 MI.getParent()->addSuccessor(It->second);
805 for (unsigned i = MI.getNumOperands() - 1; i > 1; --i)
806 MI.removeOperand(i);
808 MI.addOperand(MO);
809 if (MachineInstr *Next = MI.getNextNode()) {
812 Next = MI.getNextNode();