Lines Matching full:mi
39 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
40 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
41 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
43 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
44 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
45 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
67 // Tie operands if MI has become a two-address instruction.
68 static void tieOpsIfNeeded(MachineInstr &MI) {
69 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&
70 !MI.getOperand(0).isTied())
71 MI.tieOperands(0, 1);
74 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
77 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
79 Register Reg = MI.getOperand(0).getReg();
94 uint64_t Imm = MI.getOperand(1).getImm();
96 MI.setDesc(TII->get(LLIxL));
97 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
101 MI.setDesc(TII->get(LLIxH));
102 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
103 MI.getOperand(1).setImm(Imm >> 16);
109 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
111 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
112 MI.setDesc(TII->get(Opcode));
118 // Change MI's opcode to Opcode if register operands 0 and 1 have a
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
121 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
122 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
123 MI.setDesc(TII->get(Opcode));
129 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
131 // with op 1, if MI becomes 2-address.
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
133 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
135 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
136 MI.setDesc(TII->get(Opcode));
137 tieOpsIfNeeded(MI);
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
146 if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) {
147 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
154 // MI is a vector-style conversion instruction with the operand order:
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
159 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
160 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
161 MachineOperand Dest(MI.getOperand(0));
162 MachineOperand Src(MI.getOperand(1));
163 MachineOperand Suppress(MI.getOperand(2));
164 MachineOperand Mode(MI.getOperand(3));
165 MI.removeOperand(3);
166 MI.removeOperand(2);
167 MI.removeOperand(1);
168 MI.removeOperand(0);
169 MI.setDesc(TII->get(Opcode));
170 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {
181 MachineOperand &DstMO = MI.getOperand(0);
182 MachineOperand &LHSMO = MI.getOperand(1);
183 MachineOperand &RHSMO = MI.getOperand(2);
184 MachineOperand &AccMO = MI.getOperand(3);
193 MI.removeOperand(3);
194 MI.removeOperand(2);
195 MI.removeOperand(1);
196 MI.setDesc(TII->get(Opcode));
197 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
215 for (MachineInstr &MI : llvm::reverse(MBB)) {
216 switch (MI.getOpcode()) {
218 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
222 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
226 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
230 Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
234 Changed |= shortenOn001(MI, SystemZ::DDBR);
238 Changed |= shortenOn001(MI, SystemZ::DEBR);
242 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
246 Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
250 Changed |= shortenOn01(MI, SystemZ::LDEBR);
254 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
258 Changed |= shortenOn001(MI, SystemZ::MDBR);
262 Changed |= shortenOn001(MI, SystemZ::MEEBR);
266 Changed |= shortenFusedFPOp(MI, SystemZ::MADBR);
270 Changed |= shortenFusedFPOp(MI, SystemZ::MAEBR);
274 Changed |= shortenFusedFPOp(MI, SystemZ::MSDBR);
278 Changed |= shortenFusedFPOp(MI, SystemZ::MSEBR);
282 Changed |= shortenOn01(MI, SystemZ::LCDFR);
286 Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
290 Changed |= shortenOn01(MI, SystemZ::LNDFR);
294 Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
298 Changed |= shortenOn01(MI, SystemZ::LPDFR);
302 Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
306 Changed |= shortenOn01(MI, SystemZ::SQDBR);
310 Changed |= shortenOn01(MI, SystemZ::SQEBR);
314 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
318 Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
322 Changed |= shortenOn01(MI, SystemZ::CDBR);
326 Changed |= shortenOn01(MI, SystemZ::CEBR);
330 Changed |= shortenOn01(MI, SystemZ::KDBR);
334 Changed |= shortenOn01(MI, SystemZ::KEBR);
339 Changed |= shortenOn0(MI, SystemZ::LDE32);
343 Changed |= shortenOn0(MI, SystemZ::STE);
347 Changed |= shortenOn0(MI, SystemZ::LD);
351 Changed |= shortenOn0(MI, SystemZ::STD);
355 int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
359 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
360 (!MI.isCommutable() ||
361 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
362 !TII->commuteInstruction(MI, false, 1, 2)))
365 MI.setDesc(TII->get(TwoOperandOpcode));
366 MI.tieOperands(0, 1);
372 MachineOperand &ImmMO = MI.getOperand(3);
380 LiveRegs.stepBackward(MI);