Lines Matching full:mi
66 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
68 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
70 MachineBasicBlock *MBB = MI->getParent();
75 MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
76 MachineInstr *LowPartMI = &*MI;
102 if (MI->mayStore()) {
107 // If Reg128 was killed, set kill flag on MI.
115 return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
116 RI.regsOverlap(Reg, MI->getOperand(3).getReg());
131 // Split ADJDYNALLOC instruction MI.
132 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
133 MachineBasicBlock *MBB = MI->getParent();
136 MachineOperand &OffsetMO = MI->getOperand(2);
145 MI->setDesc(get(NewOpcode));
149 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
153 // MI has the same kind of operand as LowOpcode, so needs to be converted
155 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
158 Register Reg = MI.getOperand(0).getReg();
160 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
162 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
165 // MI is a three-operand RIE-style pseudo instruction. Replace it with
169 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
172 Register DestReg = MI.getOperand(0).getReg();
173 Register SrcReg = MI.getOperand(1).getReg();
177 MI.setDesc(get(LowOpcodeK));
180 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
181 SystemZ::LR, 32, MI.getOperand(1).isKill(),
182 MI.getOperand(1).isUndef());
183 MI.getOperand(1).setReg(DestReg);
185 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
186 MI.tieOperands(0, 1);
190 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
193 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
195 Register Reg = MI.getOperand(0).getReg();
198 MI.getOperand(2).getImm());
199 MI.setDesc(get(Opcode));
202 // MI is a load-on-condition pseudo instruction with a single register
205 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
207 Register Reg = MI.getOperand(0).getReg();
209 MI.setDesc(get(Opcode));
212 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
215 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
218 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
219 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
220 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
223 for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2))
226 MI.eraseFromParent();
229 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
230 MachineBasicBlock *MBB = MI->getParent();
232 const Register Reg64 = MI->getOperand(0).getReg();
239 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
244 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
250 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
254 MI->setDesc(get(SystemZ::LG));
255 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
290 MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
294 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
296 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
297 return MI;
300 switch (MI.getOpcode()) {
309 auto &WorkingMI = cloneIfNew(MI);
318 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
322 // If MI is a simple load or store for a frame object, return the register
327 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
329 const MCInstrDesc &MCID = MI.getDesc();
330 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
331 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
332 FrameIndex = MI.getOperand(1).getIndex();
333 return MI.getOperand(0).getReg();
338 Register SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
340 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
343 Register SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
345 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
348 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
352 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
353 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
354 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
355 MI.getOperand(4).getImm() != 0)
359 int64_t Length = MI.getOperand(2).getImm();
360 unsigned FI1 = MI.getOperand(0).getIndex();
361 unsigned FI2 = MI.getOperand(3).getIndex();
533 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
536 assert(MI.isCompare() && "Caller should have checked for a comparison");
538 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
539 MI.getOperand(1).isImm()) {
540 SrcReg = MI.getOperand(0).getReg();
542 Value = MI.getOperand(1).getImm();
626 MachineInstr *SystemZInstrInfo::optimizeLoadInstr(MachineInstr &MI,
639 MI.findRegisterUseOperandIdx(FoldAsLoadDefReg, /*TRI=*/nullptr);
640 assert(UseOpIdx != -1 && "Expected FoldAsLoadDefReg to be used by MI.");
644 foldMemoryOperand(MI, {((unsigned)UseOpIdx)}, *DefMI)) {
758 bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
759 unsigned Opcode = MI.getOpcode();
806 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
811 unsigned Opcode = MI.getOpcode();
813 MI.setDesc(get(SystemZ::CondTrap));
814 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
820 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
822 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
829 MachineOperand FirstOp = MI.getOperand(0);
830 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
831 MI.removeOperand(1);
832 MI.removeOperand(0);
833 MI.setDesc(get(SystemZ::CallBRCL));
834 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
843 MachineOperand Target = MI.getOperand(0);
844 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
845 MI.removeOperand(1);
846 MI.removeOperand(0);
847 MI.setDesc(get(SystemZ::CallBCR));
848 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1022 // Return true if MI is a simple load or store with a 12-bit displacement
1024 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
1025 const MCInstrDesc &MCID = MI->getDesc();
1027 isUInt<12>(MI->getOperand(2).getImm()) &&
1028 MI->getOperand(3).getReg() == 0);
1078 SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
1080 MachineBasicBlock *MBB = MI.getParent();
1084 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) {
1085 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
1101 MachineOperand &Dest = MI.getOperand(0);
1102 MachineOperand &Src = MI.getOperand(1);
1104 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1113 unsigned NumOps = MI.getNumOperands();
1115 MachineOperand &Op = MI.getOperand(I);
1117 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
1121 LIS->ReplaceMachineInstrInMaps(MI, *MIB);
1122 transferDeadCC(&MI, MIB);
1191 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1198 unsigned Opcode = MI.getOpcode();
1205 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1214 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1217 MI.getDebugLoc(), get(SystemZ::AGSI))
1220 .addImm(MI.getOperand(2).getImm());
1236 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1240 isInt<8>(MI.getOperand(2).getImm())) {
1244 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1247 .addImm(MI.getOperand(2).getImm());
1248 transferDeadCC(&MI, BuiltMI);
1249 transferMIFlag(&MI, BuiltMI, MachineInstr::NoSWrap);
1254 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1256 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1260 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1263 .addImm((int8_t)MI.getOperand(2).getImm());
1264 transferDeadCC(&MI, BuiltMI);
1269 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1271 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1275 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1278 .addImm((int8_t)-MI.getOperand(2).getImm());
1279 transferDeadCC(&MI, BuiltMI);
1293 if (isUInt<16>(MI.getOperand(1).getImm()))
1297 if (isUInt<16>(MI.getOperand(1).getImm()))
1303 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1307 .addImm(MI.getOperand(1).getImm());
1316 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1318 .add(MI.getOperand(1))
1327 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1329 .add(MI.getOperand(0))
1349 if (OpNum == 0 && MI.hasOneMemOperand()) {
1350 MachineMemOperand *MMO = *MI.memoperands_begin();
1353 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1354 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1359 .add(MI.getOperand(1))
1360 .addImm(MI.getOperand(2).getImm())
1364 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1365 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1367 .add(MI.getOperand(1))
1368 .addImm(MI.getOperand(2).getImm())
1379 // CC if it is live and MI does not define it.
1380 unsigned NumOps = MI.getNumExplicitOperands();
1383 (CCLiveAtMI && !MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr) &&
1389 const MCInstrDesc &MCID = MI.getDesc();
1396 Register Reg = MI.getOperand(I).getReg();
1411 Register DstReg = VRM->getPhys(MI.getOperand(0).getReg());
1412 Register AccReg = VRM->getPhys(MI.getOperand(3).getReg());
1419 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1420 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1421 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1422 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1423 OpNum == 0 && prepareCompareSwapOperands(MI))
1427 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1428 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1429 assert(MI.getNumOperands() == 6 && NumOps == 5 &&
1442 Register DstReg = MI.getOperand(0).getReg();
1445 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1446 : ((OpNum == 1 && MI.isCommutable())
1447 ? MI.getOperand(2).getReg()
1464 MI.getDebugLoc(), get(MemOpcode));
1465 if (MI.isCompare()) {
1467 MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
1470 MIB.add(MI.getOperand(0));
1471 MIB.add(MI.getOperand(3));
1472 MIB.add(MI.getOperand(OpNum == 1 ? 2 : 1));
1475 MIB.add(MI.getOperand(0));
1477 MIB.add(MI.getOperand(2));
1480 MIB.add(MI.getOperand(I));
1486 unsigned CCValid = MI.getOperand(NumOps).getImm();
1487 unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
1492 (!MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr) ||
1493 MI.registerDefIsDead(SystemZ::CC, /*TRI=*/nullptr))) {
1511 transferDeadCC(&MI, MIB);
1512 transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
1513 transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
1521 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1525 MachineBasicBlock *MBB = MI.getParent();
1536 RegMemOpcode = MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB
1537 : MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB
1538 : MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
1544 RegMemOpcode = MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB
1545 : MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB
1546 : MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
1558 assert(LoadMI.getParent() == MI.getParent() && "Assuming a local fold.");
1576 if (Ops.size() != 1 || FoldAsLoadDefReg != MI.getOperand(Ops[0]).getReg())
1578 Register DstReg = MI.getOperand(0).getReg();
1579 MachineOperand LHS = MI.getOperand(1);
1580 MachineOperand RHS = MI.getOperand(2);
1590 BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(RegMemOpcode), DstReg)
1598 transferMIFlag(&MI, MIB, MachineInstr::NoFPExcept);
1603 bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1604 switch (MI.getOpcode()) {
1606 splitMove(MI, SystemZ::LG);
1610 splitMove(MI, SystemZ::STG);
1614 splitMove(MI, SystemZ::LD);
1618 splitMove(MI, SystemZ::STD);
1622 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1626 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1630 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1634 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1638 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1642 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1646 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1650 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1654 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1658 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1662 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1666 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1670 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1674 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1678 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1682 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1686 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1690 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1694 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1698 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1702 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1706 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1710 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1714 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1718 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1722 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1726 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1730 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1734 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1738 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1742 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1746 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1750 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1754 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1758 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1759 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1761 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1763 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1764 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1770 splitAdjDynAlloc(MI);
1774 expandLoadStackGuard(&MI);
1782 unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1783 if (MI.isInlineAsm()) {
1784 const MachineFunction *MF = MI.getParent()->getParent();
1785 const char *AsmStr = MI.getOperand(0).getSymbolName();
1788 else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1789 return PatchPointOpers(&MI).getNumPatchBytes();
1790 else if (MI.getOpcode() == SystemZ::STACKMAP)
1791 return MI.getOperand(1).getImm();
1792 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1795 return MI.getDesc().getSize();
1799 SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1800 switch (MI.getOpcode()) {
1806 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1810 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1811 MI.getOperand(1).getImm(), &MI.getOperand(2));
1816 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1820 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1825 MI.getOperand(2).getImm(), &MI.getOperand(3));
1830 MI.getOperand(2).getImm(), &MI.getOperand(3));
1835 MI.getOperand(2).getImm(), &MI.getOperand(3));
1840 MI.getOperand(2).getImm(), &MI.getOperand(3));
1896 const MachineInstr *MI) const {
1920 if (MI && MI->getOperand(0).isReg()) {
1921 Register Reg = MI->getOperand(0).getReg();
2002 const MachineInstr *MI) const {
2006 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
2011 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
2018 if (!(MI && MI->getOperand(3).getReg() == 0))
2124 for (MachineInstr &MI : llvm::make_range(std::next(MBBI), MBB->end())) {
2125 if (MI.readsRegister(SystemZ::CC, /*TRI=*/nullptr)) {
2126 unsigned Flags = MI.getDesc().TSFlags;
2128 CCUsers.push_back(&MI);
2132 if (MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr)) {
2171 MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
2175 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2180 MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
2183 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2238 bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
2240 const MCInstrDesc &MCID = MI.getDesc();
2241 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
2244 const MachineOperand &Op = MI.getOperand(I);
2296 bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
2300 if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {
2301 ImmVal = MI.getOperand(1).getImm();