Home
last modified time | relevance | path

Searched full:into (Results 1 – 25 of 7096) sorted by relevance

12345678910>>...284

/llvm-project/llvm/test/MC/Mips/
H A Dset-nomacro.s3 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
81 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
83 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
88 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
92 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
99 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dzcmp-prolog-epilog-crash.mir66 ; CHECK-NEXT: SB $x0, $x2, 31 :: (store (s8) into %stack.0 + 31)
67 ; CHECK-NEXT: SB $x0, $x2, 30 :: (store (s8) into %stack.0 + 30)
68 ; CHECK-NEXT: SB $x0, $x2, 29 :: (store (s8) into %stack.0 + 29)
69 ; CHECK-NEXT: SB $x0, $x2, 28 :: (store (s8) into %stack.0 + 28)
70 ; CHECK-NEXT: SB $x0, $x2, 27 :: (store (s8) into %stack.0 + 27)
71 ; CHECK-NEXT: SB $x0, $x2, 26 :: (store (s8) into %stack.0 + 26)
72 ; CHECK-NEXT: SB $x0, $x2, 25 :: (store (s8) into %stack.0 + 25)
73 ; CHECK-NEXT: SB $x0, $x2, 24 :: (store (s8) into %stack.0 + 24)
74 ; CHECK-NEXT: SB $x0, $x2, 23 :: (store (s8) into %stack.0 + 23)
75 ; CHECK-NEXT: SB $x0, $x2, 22 :: (store (s8) into
[all...]
H A Dstack-slot-coloring.mir96 ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1)
98 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
100 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
102 ; CHECK-NEXT: SW killed renamable $x1, %stack.1, 0 :: (store (s32) into %stack.1)
104 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
106 ; CHECK-NEXT: SW killed renamable $x1, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
107 ; CHECK-NEXT: SW $x10, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
108 ; CHECK-NEXT: SW $x11, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
109 ; CHECK-NEXT: SW $x12, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
110 ; CHECK-NEXT: SW $x13, %stack.0.a, 0 :: (volatile store (s32) into %ir.a)
[all …]
H A Dmake-compressible.mir311 ; RV32-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a)
312 ; RV32-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b)
313 ; RV32-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c)
320 ; RV64-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a)
321 ; RV64-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b)
322 ; RV64-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c)
324 SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
325 SW $x0, killed renamable $x11, 0 :: (store (s32) into %ir.b)
326 SW $x0, killed renamable $x12, 0 :: (store (s32) into %ir.c)
341 ; RV32C-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
[all …]
H A Dmake-compressible-rv64.mir115 ; CHECK-NEXT: SD $x13, killed renamable $x10, 0 :: (store (s64) into %ir.a)
116 ; CHECK-NEXT: SD $x13, killed renamable $x11, 0 :: (store (s64) into %ir.b)
117 ; CHECK-NEXT: SD $x13, killed renamable $x12, 0 :: (store (s64) into %ir.c)
119 SD $x0, killed renamable $x10, 0 :: (store (s64) into %ir.a)
120 SD $x0, killed renamable $x11, 0 :: (store (s64) into %ir.b)
121 SD $x0, killed renamable $x12, 0 :: (store (s64) into %ir.c)
137 ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p)
139 ; CHECK-NEXT: SD killed renamable $x10, $x11, 0 :: (volatile store (s64) into %ir.p)
141 ; CHECK-NEXT: SD killed renamable $x10, killed $x11, 0 :: (volatile store (s64) into %ir.p)
144 SD killed renamable $x10, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
[all …]
/llvm-project/clang-tools-extra/test/clang-tidy/checkers/bugprone/
H A Doptional-value-conversion.cpp72 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
75 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
78 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
81 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
84 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
87 … :[[@LINE-1]]:21: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
90 … :[[@LINE-1]]:19: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
93 … :[[@LINE-1]]:19: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
96 … :[[@LINE-1]]:19: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
99 … :[[@LINE-1]]:19: warning: conversion from 'std::optional<int>' into 'int' and back into 'std::opt… in incorrect()
[all …]
/llvm-project/mlir/test/Integration/Dialect/Vector/CPU/
H A Dsparse-saxpy-jagged-matvec.mlir25 // using fixed length vectors and no explicit pointer indexing into the
61 : memref<?xf32>, vector<8xi32>, vector<8xi1>, vector<8xf32> into vector<8xf32>
114 %0 = vector.insert %f3, %vf1[3] : f32 into vector<8xf32>
115 %1 = vector.insert %f5, %0[4] : f32 into vector<8xf32>
116 %2 = vector.insert %f3, %1[5] : f32 into vector<8xf32>
117 %3 = vector.insert %f4, %2[6] : f32 into vector<8xf32>
118 %4 = vector.insert %f3, %3[7] : f32 into vector<8xf32>
121 %5 = vector.insert %f2, %vf1[0] : f32 into vector<8xf32>
122 %6 = vector.insert %f8, %5[1] : f32 into vector<8xf32>
123 %7 = vector.insert %f2, %6[2] : f32 into vecto
[all...]
H A Dsparse-dot-matvec.mlir25 // using fixed length vectors and no explicit pointer indexing into the
68 : memref<?xf32>, vector<4xi32>, vector<4xi1>, vector<4xf32> into vector<4xf32>
69 %1 = vector.contract #dot_trait %aval, %0, %f0 : vector<4xf32>, vector<4xf32> into f32
120 %0 = vector.insert %f2, %vf1[1] : f32 into vector<4xf32>
123 %1 = vector.insert %f8, %vf1[1] : f32 into vector<4xf32>
124 %2 = vector.insert %f3, %1[2] : f32 into vector<4xf32>
127 %3 = vector.insert %f2, %vf1[1] : f32 into vector<4xf32>
128 %4 = vector.insert %f6, %3[2] : f32 into vector<4xf32>
129 %5 = vector.insert %f2, %4[3] : f32 into vector<4xf32>
132 %6 = vector.insert %f3, %vf1[0] : f32 into vecto
[all...]
H A Dreductions-i32.mlir19 %v1 = vector.insert %i2, %v0[1] : i32 into vector<10xi32>
20 %v2 = vector.insert %i3, %v1[2] : i32 into vector<10xi32>
21 %v3 = vector.insert %i4, %v2[3] : i32 into vector<10xi32>
22 %v4 = vector.insert %i5, %v3[4] : i32 into vector<10xi32>
23 %v5 = vector.insert %i6, %v4[5] : i32 into vector<10xi32>
24 %v6 = vector.insert %i7, %v5[6] : i32 into vector<10xi32>
25 %v7 = vector.insert %i8, %v6[7] : i32 into vector<10xi32>
26 %v8 = vector.insert %i9, %v7[8] : i32 into vector<10xi32>
27 %v9 = vector.insert %i10, %v8[9] : i32 into vector<10xi32>
36 %0 = vector.reduction <add>, %v9 : vector<10xi32> into i3
[all...]
H A Dreductions-i64.mlir19 %v1 = vector.insert %i2, %v0[1] : i64 into vector<10xi64>
20 %v2 = vector.insert %i3, %v1[2] : i64 into vector<10xi64>
21 %v3 = vector.insert %i4, %v2[3] : i64 into vector<10xi64>
22 %v4 = vector.insert %i5, %v3[4] : i64 into vector<10xi64>
23 %v5 = vector.insert %i6, %v4[5] : i64 into vector<10xi64>
24 %v6 = vector.insert %i7, %v5[6] : i64 into vector<10xi64>
25 %v7 = vector.insert %i8, %v6[7] : i64 into vector<10xi64>
26 %v8 = vector.insert %i9, %v7[8] : i64 into vector<10xi64>
27 %v9 = vector.insert %i10, %v8[9] : i64 into vector<10xi64>
36 %0 = vector.reduction <add>, %v9 : vector<10xi64> into i6
[all...]
H A Dcontraction.mlir154 %a = vector.insert %f2, %0[1] : f32 into vector<2xf32>
156 %b = vector.insert %f4, %1[1] : f32 into vector<2xf32>
158 %c = vector.insert %f6, %2[1] : f32 into vector<2xf32>
160 %d = vector.insert %f8, %3[1] : f32 into vector<2xf32>
176 %5 = vector.insert %a, %4[0] : vector<2xf32> into vector<2x2xf32>
177 %A = vector.insert %b, %5[1] : vector<2xf32> into vector<2x2xf32>
179 %7 = vector.insert %c, %6[0] : vector<2xf32> into vector<2x2xf32>
180 %B = vector.insert %d, %7[1] : vector<2xf32> into vector<2x2xf32>
182 %9 = vector.insert %a, %8[0] : vector<2xf32> into vector<3x2xf32>
183 %10 = vector.insert %b, %9[1] : vector<2xf32> into vecto
[all...]
H A Dreductions-f64.mlir19 %v1 = vector.insert %f2, %v0[1] : f64 into vector<10xf64>
20 %v2 = vector.insert %f3, %v1[2] : f64 into vector<10xf64>
21 %v3 = vector.insert %f4, %v2[3] : f64 into vector<10xf64>
22 %v4 = vector.insert %f5, %v3[4] : f64 into vector<10xf64>
23 %v5 = vector.insert %f6, %v4[5] : f64 into vector<10xf64>
24 %v6 = vector.insert %f7, %v5[6] : f64 into vector<10xf64>
25 %v7 = vector.insert %f8, %v6[7] : f64 into vector<10xf64>
26 %v8 = vector.insert %f9, %v7[8] : f64 into vector<10xf64>
27 %v9 = vector.insert %f10, %v8[9] : f64 into vector<10xf64>
36 %0 = vector.reduction <add>, %v9 : vector<10xf64> into f6
[all...]
H A Dreductions-f32.mlir19 %v1 = vector.insert %f2, %v0[1] : f32 into vector<10xf32>
20 %v2 = vector.insert %f3, %v1[2] : f32 into vector<10xf32>
21 %v3 = vector.insert %f4, %v2[3] : f32 into vector<10xf32>
22 %v4 = vector.insert %f5, %v3[4] : f32 into vector<10xf32>
23 %v5 = vector.insert %f6, %v4[5] : f32 into vector<10xf32>
24 %v6 = vector.insert %f7, %v5[6] : f32 into vector<10xf32>
25 %v7 = vector.insert %f8, %v6[7] : f32 into vector<10xf32>
26 %v8 = vector.insert %f9, %v7[8] : f32 into vector<10xf32>
27 %v9 = vector.insert %f10, %v8[9] : f32 into vector<10xf32>
36 %0 = vector.reduction <add>, %v9 : vector<10xf32> into f3
[all...]
/llvm-project/flang/test/Semantics/OpenMP/
H A Dinvalid-branch.f904 ! Check invalid branches into or out of OpenMP structured blocks.
10 !CHECK: invalid branch into an OpenMP structured block
11 !CHECK: In the enclosing PARALLEL directive branched into
19 !CHECK: invalid branch into an OpenMP structured block
20 !CHECK: In the enclosing PARALLEL directive branched into
44 !CHECK: invalid branch into an OpenMP structured block
45 !CHECK: In the enclosing PARALLEL directive branched into
48 !CHECK: invalid branch into an OpenMP structured block
49 !CHECK: In the enclosing PARALLEL directive branched into
63 !CHECK: invalid branch into a
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Daccvgpr-spill-scc-clobber.mir26 ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
96 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
97 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
98 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
99 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
100 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
101 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
102 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
103 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
104 ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into
[all...]
/llvm-project/llvm/test/Transforms/Inline/ARM/
H A Dinline-fp.ll7 ; NOFP-DAG: 'single' not inlined into 'test_single' because too costly to inline (cost=125, thresho…
8 ; NOFP-DAG: 'single' not inlined into 'test_single' because too costly to inline (cost=125, thresho…
9 ; NOFP-DAG: 'single_cheap' inlined into 'test_single_cheap' with (cost=-15, threshold=75)
10 ; NOFP-DAG: 'single_cheap' inlined into 'test_single_cheap' with (cost=-15015, threshold=75)
11 ; NOFP-DAG: 'double' not inlined into 'test_double' because too costly to inline (cost=125, thresho…
12 ; NOFP-DAG: 'double' not inlined into 'test_double' because too costly to inline (cost=125, thresho…
13 ; NOFP-DAG: 'single_force_soft' not inlined into 'test_single_force_soft' because too costly to inl…
14 ; NOFP-DAG: 'single_force_soft' not inlined into 'test_single_force_soft' because too costly to inl…
15 ; NOFP-DAG: 'single_force_soft_fneg' not inlined into 'test_single_force_soft_fneg' because too cos…
16 ; NOFP-DAG: 'single_force_soft_fneg' not inlined into 'test_single_force_soft_fneg' because too cos…
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dframe-26.mir77 STG killed renamable $r6d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
80 STG renamable $r0d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
91 …STE killed renamable $f0s, undef renamable $r1d, 0, $noreg :: (volatile store (s32) into `ptr unde…
96 STG renamable $r4d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
102 STG renamable $r10d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
107 STG killed renamable $r9d, $noreg, 0, $noreg :: (store (s64) into `ptr null`)
108 STG killed renamable $r3d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
109 STG killed renamable $r14d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
110 STG killed renamable $r7d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
111 STG killed renamable $r1d, undef renamable $r1d, 0, $noreg :: (store (s64) into `ptr undef`)
[all …]
H A Dfp-conv-17.mir149 STE %2, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
150 STE %3, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
151 STE %4, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
152 STE %5, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
153 STE %6, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
154 STE %7, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
155 STE %8, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
156 STE %9, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
157 STE %10, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
158 STE %11, %1, 0, $noreg :: (volatile store (s32) into %ir.ptr2)
[all …]
/llvm-project/mlir/test/Integration/Dialect/Vector/CPU/X86Vector/
H A Dvp2intersect-i32.mlir18 %v1 = vector.insert %i2, %v0[1] : i32 into vector<16xi32>
19 %v2 = vector.insert %i3, %v1[4] : i32 into vector<16xi32>
20 %v3 = vector.insert %i4, %v2[6] : i32 into vector<16xi32>
21 %v4 = vector.insert %i5, %v3[7] : i32 into vector<16xi32>
22 %v5 = vector.insert %i0, %v4[10] : i32 into vector<16xi32>
23 %v6 = vector.insert %i0, %v5[12] : i32 into vector<16xi32>
24 %v7 = vector.insert %i3, %v6[13] : i32 into vector<16xi32>
25 %v8 = vector.insert %i3, %v7[14] : i32 into vector<16xi32>
26 %v9 = vector.insert %i0, %v8[15] : i32 into vector<16xi32>
31 %w1 = vector.insert %i2, %w0[4] : i32 into vector<16xi32>
[all …]
/llvm-project/mlir/test/Dialect/MemRef/
H A Dops.mlir305 // CHECK-SAME: memref<3x4x5xf32> into memref<12x5xf32>
307 memref<3x4x5xf32> into memref<12x5xf32>
310 // CHECK-SAME: memref<12x5xf32> into memref<3x4x5xf32>
312 memref<12x5xf32> into memref<3x4x5xf32>
315 // CHECK-SAME: memref<3x4x5xf32> into memref<3x20xf32>
317 memref<3x4x5xf32> into memref<3x20xf32>
320 // CHECK-SAME: memref<3x20xf32> into memref<3x4x5xf32>
322 memref<3x20xf32> into memref<3x4x5xf32>
325 // CHECK-SAME: memref<3x4x5xf32> into memref<60xf32>
327 memref<3x4x5xf32> into memre
[all...]
/llvm-project/llvm/include/llvm/DebugInfo/GSYM/
H A DFileWriter.h37 /// Write a single uint8_t value into the stream at the current file
40 /// \param Value The value to write into the stream.
43 /// Write a single uint16_t value into the stream at the current file
47 /// \param Value The value to write into the stream.
50 /// Write a single uint32_t value into the stream at the current file
54 /// \param Value The value to write into the stream.
57 /// Write a single uint64_t value into the stream at the current file
61 /// \param Value The value to write into the stream.
64 /// Write the value into the stream encoded using signed LEB128 at the
67 /// \param Value The value to write into the stream.
[all …]
/llvm-project/clang/test/OpenMP/
H A Dcancellation_point_messages.cpp13 …t' directives are prohibited; perhaps you forget to enclose the directive into a region?}} expecte… in main()
19 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
20 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
21 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
22 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
24 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
51 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
53 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
56 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
60 …tion point' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
[all …]
H A Dcancel_messages.cpp13 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
19 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
20 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
21 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
22 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
24 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
51 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
53 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
56 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
60 …omp cancel' directives are prohibited; perhaps you forget to enclose the directive into a region?}} in main()
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Dpr30821.mir64 ; data into $xmm[0-14] and volatile storing them later, leaving regalloc only
94 …MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %13 :: (volatile store (s128) into %ir.india)
96 …ia, 1, $noreg, 0, $noreg, killed renamable $xmm{{[0-9]+}} :: (volatile store (s128) into %ir.india)
99 ….2.india, 1, $noreg, 0, $noreg, killed %1 :: (volatile dereferenceable store (s128) into %ir.india)
107 …MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %23 :: (volatile store (s128) into %ir.india)
110 …ia, 1, $noreg, 0, $noreg, killed renamable $xmm{{[0-9]+}} :: (volatile store (s128) into %ir.india)
112 ….2.india, 1, $noreg, 0, $noreg, killed %2 :: (volatile dereferenceable store (s128) into %ir.india)
120 VMOVSDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %33 :: (store (s64) into %ir.india)
124 …Smr %stack.3, 1, $noreg, 0, $noreg, killed renamable $xmm{{[0-9]+}} :: (store (s128) into %stack.3)
127 ….2.india, 1, $noreg, 0, $noreg, killed %3 :: (volatile dereferenceable store (s128) into %ir.india)
[all …]
/llvm-project/mlir/test/Dialect/Vector/
H A Dchained-vector-reduction-folding.mlir6 // CHECK-NEXT: %[[RES:.+]] = vector.reduction <add>, %[[ARG0]], %[[CST]] : vector<8xf32> into…
10 %0 = vector.reduction <add>, %arg0, %cst0 : vector<8xf32> into f32
18 // CHECK-NEXT: %[[RES:.+]] = vector.reduction <add>, %[[ADD]], %[[CST]] : vector<8xf32> into …
22 %0 = vector.reduction <add>, %arg0, %cst0 : vector<8xf32> into f32
23 %1 = vector.reduction <add>, %arg1, %0 : vector<8xf32> into f32
30 // CHECK-NEXT: %[[RES:.+]] = vector.reduction <add>, %[[ADD]] : vector<8xf32> into f32
33 %0 = vector.reduction <add>, %arg0 : vector<8xf32> into f32
34 %1 = vector.reduction <add>, %arg1, %0 : vector<8xf32> into f32
41 // CHECK-NEXT: %[[RES:.+]] = vector.reduction <add>, %[[ADD]] : vector<8xf32> into f32
46 %0 = vector.reduction <add>, %x : vector<8xf32> into f32
[all …]

12345678910>>...284