xref: /llvm-project/mlir/test/Integration/Dialect/Vector/CPU/reductions-i64.mlir (revision eb206e9ea84eff0a0596fed2de8316d924f946d1)
1// RUN: mlir-opt %s -test-lower-to-llvm  | \
2// RUN: mlir-runner -e entry -entry-point-result=void  \
3// RUN:   -shared-libs=%mlir_c_runner_utils | \
4// RUN: FileCheck %s
5
6func.func @entry() {
7  // Construct test vector.
8  %i1 = arith.constant 1: i64
9  %i2 = arith.constant 2: i64
10  %i3 = arith.constant 3: i64
11  %i4 = arith.constant 4: i64
12  %i5 = arith.constant 5: i64
13  %i6 = arith.constant -1: i64
14  %i7 = arith.constant -2: i64
15  %i8 = arith.constant -4: i64
16  %i9 = arith.constant -80: i64
17  %i10 = arith.constant -16: i64
18  %v0 = vector.broadcast %i1 : i64 to vector<10xi64>
19  %v1 = vector.insert %i2, %v0[1] : i64 into vector<10xi64>
20  %v2 = vector.insert %i3, %v1[2] : i64 into vector<10xi64>
21  %v3 = vector.insert %i4, %v2[3] : i64 into vector<10xi64>
22  %v4 = vector.insert %i5, %v3[4] : i64 into vector<10xi64>
23  %v5 = vector.insert %i6, %v4[5] : i64 into vector<10xi64>
24  %v6 = vector.insert %i7, %v5[6] : i64 into vector<10xi64>
25  %v7 = vector.insert %i8, %v6[7] : i64 into vector<10xi64>
26  %v8 = vector.insert %i9, %v7[8] : i64 into vector<10xi64>
27  %v9 = vector.insert %i10, %v8[9] : i64 into vector<10xi64>
28  vector.print %v9 : vector<10xi64>
29  //
30  // test vector:
31  //
32  // CHECK: ( 1, 2, 3, 4, 5, -1, -2, -4, -80, -16 )
33
34  // Various vector reductions. Not full functional unit tests, but
35  // a simple integration test to see if the code runs end-to-end.
36  %0 = vector.reduction <add>, %v9 : vector<10xi64> into i64
37  vector.print %0 : i64
38  // CHECK: -88
39  %1 = vector.reduction <mul>, %v9 : vector<10xi64> into i64
40  vector.print %1 : i64
41  // CHECK: -1228800
42  %2 = vector.reduction <minsi>, %v9 : vector<10xi64> into i64
43  vector.print %2 : i64
44  // CHECK: -80
45  %3 = vector.reduction <maxsi>, %v9 : vector<10xi64> into i64
46  vector.print %3 : i64
47  // CHECK: 5
48  %4 = vector.reduction <and>, %v9 : vector<10xi64> into i64
49  vector.print %4 : i64
50  // CHECK: 0
51  %5 = vector.reduction <or>, %v9 : vector<10xi64> into i64
52  vector.print %5 : i64
53  // CHECK: -1
54  %6 = vector.reduction <xor>, %v9 : vector<10xi64> into i64
55  vector.print %6 : i64
56  // CHECK: -68
57
58  return
59}
60