| /freebsd-src/sys/contrib/device-tree/Bindings/display/ |
| H A D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
18 Documentation/devicetree/bindings/gpio/gpio.txt for details.
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
[all …]
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| /freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap5-l4.dtsi | 2 compatible = "ti,omap5-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_core>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
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|
| H A D | am33xx-l4.dtsi | 2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
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|
| H A D | omap4-l4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
4 power-domains = <&prm_core>;
6 clock-names = "fck";
10 reg-names = "ap", "la", "ia0";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
[all …]
|
| H A D | am437x-l4.dtsi | 2 compatible = "ti,am4-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
|
| H A D | dra7-l4.dtsi | 2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_coreaon>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment
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| /freebsd-src/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am62p.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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| H A D | k3-j721s2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controlle
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| H A D | k3-j784s4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controlle
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| /freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6dl-yapp43-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-binding
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| /freebsd-src/contrib/wpa/src/common/ |
| H A D | qca-vendor.h | 3 * Copyright (c) 2014-2017, Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2020, The Linux Foundation
5 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc.
28 * enum qca_radiotap_vendor_ids - QCA radiotap vendor namespace IDs
41 * Global NSS configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
62 * Per band NSS configuration - Applies to the 2.4 GHz or 5/6 GHz band
79 * Global chain configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
96 * Per band chain configuration - Applies to the 2.4 GHz or 5/6 GHz band
117 * Case 1: CONFIG_NSS + CONFIG_TX_NSS/RX_NSS - Only CONFIG_NSS is applied
120 * Case 2: CONFIG_NSS + CONFIG_TX_NSS + CONFIG_RX_NSS - Sam
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| /freebsd-src/sys/dev/mlx5/ |
| H A D | device.h | 1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
184 MLX5_PCI_CMD_XPORT = 7,
631 struct mlx5_eqe_gpio gpio; global() member
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| /freebsd-src/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_ec_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
214 /* [0x38] VLAN p-bits table address */
216 /* [0x3c] VLAN p-bits table data */
340 /* [0x18] TCP control bit operation for first segment */
344 /* [0x20] TCP control bit operation for last segment */
415 /* [0x0] Mask of pause_on [7:0] for the Ethernet controller ... */
421 /* [0xc] Mask for generating GPIO output XOFF indication fro ... */
422 uint32_t gpio; member
450 /* [0x1c] Mask of "pause_on" [7] for all queues */
[all …]
|
| /freebsd-src/sys/conf/ |
| H A D | NOTES | 2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
11 # Please use ``make LINT'' to create an old-style LINT file if you want to
12 # do kernel test-builds.
48 # auto-size based on physical memory.
66 # after most other flags. Here we use it to inhibit use of non-optimal
67 # gcc built-in functions (e.g., memcmp).
70 # The following is equivalent to 'config -g KERNELNAME' and creates
71 # 'kernel.debug' compiled with -g debugging as well as a normal
81 makeoptions CONF_CFLAGS=-fn
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| /freebsd-src/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
85 …USE_NUM_E::CHIP_TYPE() fuses, and as enumerated by PCC_PROD_E::CNXXXX. _ <7:0> is typically set …
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
112 …_E5 (0x1<<7) // IDSEL stepping/w…
113 …CIEIP_REG_PCIEEP_CMD_IDS_WCC_E5_SHIFT 7
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|
| /freebsd-src/sys/arm/allwinner/ |
| H A D | if_awg.c | 1 /*-
42 #include <sys/gpio.h>
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT -
1798 device_t gpio; awg_phy_reset() local
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| /freebsd-src/sys/dev/bxe/ |
| H A D | ecore_hsi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
145 /* Up to 16 bytes of NULL-terminated string */
164 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
170 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
172 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
173 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
175 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
[all …]
|
| H A D | bxe.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
64 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
241 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port
16485 bxe_igu_ack_sb(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t segment,uint16_t index,uint8_t op,uint8_t update) bxe_igu_ack_sb() argument
[all...] |
| /freebsd-src/sys/dev/rtsx/ |
| H A D | rtsx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
12 * - Lutz Bichler <Lutz.Bichler@gmail.com>
73 /* The softc holds our per-instance data. */
105 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */
111 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */
136 uint8_t rtsx_cam_status; /* CAM status -
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| /freebsd-src/share/misc/ |
| H A D | pci_vendors | 5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
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| /freebsd-src/sys/dev/ral/ |
| H A D | rt2860.c | 1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
21 /*-
70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
238 struct ieee80211com *ic = &sc->sc_ic; in rt2860_attach()
242 sc->sc_dev = dev; in rt2860_attach()
243 sc->sc_debug = 0; in rt2860_attach()
245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in rt2860_attach()
248 callout_init_mtx(&sc->watchdog_c in rt2860_attach()
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| /freebsd-src/sys/contrib/dev/athk/ath10k/ |
| H A D | wmi.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
28 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
44 * variable is already 4-byte aligned by virtue of being a u32
526 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
532 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
533 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
1159 /** DFS-specific commands */
[all …]
|
| H A D | core.c | 1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
21 #include <linux/nvmem-consumer.h>
33 #include "wmi-ops.h"
65 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
78 .uart_pin = 7,
118 .uart_pin = 7,
159 .uart_pin = 7,
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|
| /freebsd-src/sys/dev/iwm/ |
| H A D | if_iwmreg.h | 10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-
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| /freebsd-src/sys/dev/bge/ |
| H A D | if_bge.c | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
19 * 4. Neither the name of the author nor the names of any co-contributors
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bi
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