Lines Matching +full:gpio +full:- +full:7 +full:- +full:segment
1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
184 MLX5_PCI_CMD_XPORT = 7,
224 MLX5_PERM_UMR_EN = 1 << 7,
256 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
270 MLX5_MKEY_MASK_PD = 1ull << 7,
291 MLX5_UMR_INLINE = (1 << 7),
295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
310 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
442 * - ctrl segment (16 bytes)
443 * - rdma segment (16 bytes)
444 * - scatter elements (16 bytes each)
446 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
525 u8 reserved1[7];
634 __be32 raw[7];
640 struct mlx5_eqe_gpio gpio;
658 __be32 rsvd2[7];
735 return (cqe->op_own >> 4);
740 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
745 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
750 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
755 return be16_to_cpu(cqe->vlan_info) & 0xfff;
760 memcpy(smac, &cqe->rss_hash_type , 4);
761 memcpy(smac + 4, &cqe->slid , 2);
766 return cqe->l4_hdr_type_etc & 0x1;
771 return cqe->tls_outer_l3_tunneled & 0x1;
776 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
869 /* This is a two bit field occupying bits 31-30.
948 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
1050 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1053 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1056 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1059 MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1063 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1067 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1070 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1073 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1076 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1079 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1082 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1085 MLX5_GET64(flow_table_nic_cap, (mdev)->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1088 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1128 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1132 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1160 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1164 (mdev)->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1168 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1172 mdev->hca_caps_cur[MLX5_CAP_PORT_SELECTION], cap)
1176 mdev->hca_caps_max[MLX5_CAP_PORT_SELECTION], cap)
1180 mdev->hca_caps_cur[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1184 mdev->hca_caps_max[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1193 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1196 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1200 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1204 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1208 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1212 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1216 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1220 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1224 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1228 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1231 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1234 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1237 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1240 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1243 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1246 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1249 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1252 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1255 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1258 MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)
1261 MLX5_GET(ipsec_cap, (mdev)->hca_caps_cur[MLX5_CAP_IPSEC], cap)
1392 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;