Lines Matching +full:gpio +full:- +full:7 +full:- +full:segment
1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
21 /*-
70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
238 struct ieee80211com *ic = &sc->sc_ic;
242 sc->sc_dev = dev;
243 sc->sc_debug = 0;
245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
249 mbufq_init(&sc->sc_snd, ifqmaxlen);
259 device_printf(sc->sc_dev,
264 sc->mac_ver = tmp >> 16;
265 sc->mac_rev = tmp & 0xffff;
267 if (sc->mac_ver != 0x2860 &&
269 sc->sc_flags |= RT2860_ADVANCED_PS;
272 rt2860_read_eeprom(sc, ic->ic_macaddr);
273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":");
282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
283 device_printf(sc->sc_dev,
289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
290 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
295 device_printf(sc->sc_dev, "could not allocate Tx pool\n");
300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
303 ic->ic_softc = sc;
304 ic->ic_name = device_get_nameunit(dev);
305 ic->ic_opmode = IEEE80211_M_STA;
306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
309 ic->ic_caps =
315 | IEEE80211_C_WDS /* 4-address traffic works */
326 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
327 ic->ic_channels);
331 ic->ic_wme.wme_update = rt2860_updateedca;
332 ic->ic_scan_start = rt2860_scan_start;
333 ic->ic_scan_end = rt2860_scan_end;
334 ic->ic_getradiocaps = rt2860_getradiocaps;
335 ic->ic_set_channel = rt2860_set_channel;
336 ic->ic_updateslot = rt2860_updateslot;
337 ic->ic_update_promisc = rt2860_update_promisc;
338 ic->ic_raw_xmit = rt2860_raw_xmit;
339 sc->sc_node_free = ic->ic_node_free;
340 ic->ic_node_free = rt2860_node_free;
341 ic->ic_newassoc = rt2860_newassoc;
342 ic->ic_transmit = rt2860_transmit;
343 ic->ic_parent = rt2860_parent;
344 ic->ic_vap_create = rt2860_vap_create;
345 ic->ic_vap_delete = rt2860_vap_delete;
348 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
350 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
356 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
363 fail3: rt2860_free_rx_ring(sc, &sc->rxq);
364 fail2: while (--qid >= 0)
365 rt2860_free_tx_ring(sc, &sc->txq[qid]);
366 fail1: mtx_destroy(&sc->sc_mtx);
374 struct ieee80211com *ic = &sc->sc_ic;
382 mbufq_drain(&sc->sc_snd);
384 rt2860_free_tx_ring(sc, &sc->txq[qid]);
385 rt2860_free_rx_ring(sc, &sc->rxq);
388 mtx_destroy(&sc->sc_mtx);
414 if (sc->sc_ic.ic_nrunning > 0)
424 struct rt2860_softc *sc = ic->ic_softc;
436 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
437 device_printf(sc->sc_dev, "only 1 vap supported\n");
444 if (TAILQ_EMPTY(&ic->ic_vaps) ||
445 ic->ic_opmode != IEEE80211_M_HOSTAP) {
446 device_printf(sc->sc_dev,
458 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
462 vap = &rvp->ral_vap;
466 rvp->ral_newstate = vap->iv_newstate;
467 vap->iv_newstate = rt2860_newstate;
469 vap->iv_update_beacon = rt2860_beacon_update;
472 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
473 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
479 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
480 ic->ic_opmode = opmode;
512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
516 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd,
521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
523 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd,
528 size, rt2860_dma_map_addr, &ring->paddr, 0);
530 device_printf(sc->sc_dev, "could not load desc DMA map\n");
534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
549 if ((data = ring->data[i]) == NULL)
552 if (data->m != NULL) {
553 bus_dmamap_sync(sc->txwi_dmat, data->map,
555 bus_dmamap_unload(sc->txwi_dmat, data->map);
556 m_freem(data->m);
557 data->m = NULL;
559 if (data->ni != NULL) {
560 ieee80211_free_node(data->ni);
561 data->ni = NULL;
564 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
565 ring->data[i] = NULL;
568 ring->queued = 0;
569 ring->cur = ring->next = 0;
578 if (ring->txd != NULL) {
579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map);
584 if (ring->desc_dmat != NULL)
585 bus_dma_tag_destroy(ring->desc_dmat);
588 if ((data = ring->data[i]) == NULL)
591 if (data->m != NULL) {
592 bus_dmamap_sync(sc->txwi_dmat, data->map,
594 bus_dmamap_unload(sc->txwi_dmat, data->map);
595 m_freem(data->m);
597 if (data->ni != NULL)
598 ieee80211_free_node(data->ni);
600 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
617 SLIST_INIT(&sc->data_pool);
619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat);
623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n");
627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr,
628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map);
630 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map,
635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0);
637 device_printf(sc->sc_dev, "could not load txwi DMA map\n");
641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
643 vaddr = sc->txwi_vaddr;
645 struct rt2860_tx_data *data = &sc->data[i];
647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map);
649 device_printf(sc->sc_dev, "could not create DMA map\n");
652 data->txwi = (struct rt2860_txwi *)vaddr;
653 data->paddr = paddr;
657 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
669 if (sc->txwi_vaddr != NULL) {
670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map,
672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map);
673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map);
675 if (sc->txwi_dmat != NULL)
676 bus_dma_tag_destroy(sc->txwi_dmat);
678 while (!SLIST_EMPTY(&sc->data_pool)) {
680 data = SLIST_FIRST(&sc->data_pool);
681 bus_dmamap_destroy(sc->txwi_dmat, data->map);
682 SLIST_REMOVE_HEAD(&sc->data_pool, next);
694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
698 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd,
703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
705 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd,
710 size, rt2860_dma_map_addr, &ring->paddr, 0);
712 device_printf(sc->sc_dev, "could not load desc DMA map\n");
716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
720 device_printf(sc->sc_dev, "could not create data DMA tag\n");
725 struct rt2860_rx_data *data = &ring->data[i];
726 struct rt2860_rxd *rxd = &ring->rxd[i];
728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
730 device_printf(sc->sc_dev, "could not create DMA map\n");
734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
735 if (data->m == NULL) {
736 device_printf(sc->sc_dev,
742 error = bus_dmamap_load(ring->data_dmat, data->map,
743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr,
746 device_printf(sc->sc_dev,
751 rxd->sdp0 = htole32(physaddr);
752 rxd->sdl0 = htole16(MCLBYTES);
755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
773 ring->cur = 0;
781 if (ring->rxd != NULL) {
782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map);
787 if (ring->desc_dmat != NULL)
788 bus_dma_tag_destroy(ring->desc_dmat);
791 struct rt2860_rx_data *data = &ring->data[i];
793 if (data->m != NULL) {
794 bus_dmamap_sync(ring->data_dmat, data->map,
796 bus_dmamap_unload(ring->data_dmat, data->map);
797 m_freem(data->m);
799 if (data->map != NULL)
800 bus_dmamap_destroy(ring->data_dmat, data->map);
802 if (ring->data_dmat != NULL)
803 bus_dma_tag_destroy(ring->data_dmat);
809 struct ieee80211com *ic = &sc->sc_ic;
813 * MAC can run into a livelock and start sending CTS-to-self frames
817 if (ic->ic_curmode != IEEE80211_M_STA) {
820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
822 DPRINTF(("CTS-to-self livelock detected\n"));
835 struct ieee80211com *ic = ni->ni_ic;
836 struct rt2860_softc *sc = ic->ic_softc;
839 wcid = IEEE80211_AID(ni->ni_associd);
840 if (isnew && ni->ni_associd != 0) {
841 sc->wcid2ni[wcid] = ni;
845 ni->ni_macaddr, IEEE80211_ADDR_LEN);
848 isnew, ether_sprintf(ni->ni_macaddr), wcid));
854 struct ieee80211com *ic = ni->ni_ic;
855 struct rt2860_softc *sc = ic->ic_softc;
858 if (ni->ni_associd != 0) {
859 wcid = IEEE80211_AID(ni->ni_associd);
864 sc->sc_node_free(ni);
872 struct rt2860_softc *sc = ic->ic_softc;
873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
887 struct rt2860_softc *sc = ic->ic_softc;
888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
902 struct ieee80211com *ic = vap->iv_ic;
903 struct rt2860_softc *sc = ic->ic_softc;
907 if (vap->iv_state == IEEE80211_S_RUN) {
912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
922 error = rvp->ral_newstate(vap, nstate, arg);
927 struct ieee80211_node *ni = vap->iv_bss;
929 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
932 rt2860_set_basicrates(sc, &ni->ni_rates);
933 rt2860_set_bssid(sc, ni->ni_bssid);
936 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
937 vap->iv_opmode == IEEE80211_M_IBSS ||
938 vap->iv_opmode == IEEE80211_M_MBSS) {
944 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ?
957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
966 /*-
967 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
970 * DATA2: 7 6 5 4
989 /* determine to which 32-bit register our 16-bit word belongs */
990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
1024 /* write address (A5-A0 or A7-A0) */
1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1026 for (; n >= 0; n--) {
1035 /* read data Q15-Q0 */
1037 for (n = 15; n >= 0; n--) {
1058 return sc->sc_srom_read(sc, addr);
1081 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
1087 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
1094 ni = sc->wcid2ni[wcid];
1100 /* update per-STA AMRR stats */
1111 txs->long_retries = 1;
1113 txs->long_retries = 0;
1114 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
1117 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
1118 txs->long_retries = 1; /* XXX */
1120 if_inc_counter(ni->ni_vap->iv_ifp,
1129 struct rt2860_tx_ring *ring = &sc->txq[qid];
1135 while (ring->next != hw) {
1136 struct rt2860_tx_data *data = ring->data[ring->next];
1139 bus_dmamap_sync(sc->txwi_dmat, data->map,
1141 bus_dmamap_unload(sc->txwi_dmat, data->map);
1142 ieee80211_tx_complete(data->ni, data->m, 0);
1143 data->ni = NULL;
1144 data->m = NULL;
1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1146 ring->data[ring->next] = NULL;
1148 ring->queued--;
1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1152 sc->sc_tx_timer = 0;
1153 if (ring->queued < RT2860_TX_RING_COUNT)
1154 sc->qfullmsk &= ~(1 << qid);
1166 if (sc->nrxchains > 1) {
1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1169 if (sc->nrxchains > 2)
1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1180 struct ieee80211com *ic = &sc->sc_ic;
1192 while (sc->rxq.cur != hw) {
1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1205 if (__predict_false(rxd->flags &
1207 counter_u64_add(ic->ic_ierrors, 1);
1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1214 ic->ic_stats.is_rx_locmicfail++;
1216 counter_u64_add(ic->ic_ierrors, 1);
1223 counter_u64_add(ic->ic_ierrors, 1);
1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1239 mtod(data->m, void *), MCLBYTES,
1243 device_get_name(sc->sc_dev));
1246 rxd->sdp0 = htole32(physaddr);
1247 counter_u64_add(ic->ic_ierrors, 1);
1255 m = data->m;
1256 data->m = m1;
1257 rxd->sdp0 = htole32(physaddr);
1262 m->m_data = (caddr_t)(rxwi + 1);
1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff;
1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1277 m->m_data += 2;
1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant);
1286 tap = &sc->sc_rxtap;
1287 tap->wr_flags = 0;
1288 tap->wr_antenna = ant;
1289 tap->wr_antsignal = nf + rssi;
1290 tap->wr_antnoise = nf;
1292 tap->wr_rate = 2;
1293 phy = le16toh(rxwi->phy);
1297 case 0: tap->wr_rate = 2; break;
1298 case 1: tap->wr_rate = 4; break;
1299 case 2: tap->wr_rate = 11; break;
1300 case 3: tap->wr_rate = 22; break;
1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1307 case 0: tap->wr_rate = 12; break;
1308 case 1: tap->wr_rate = 18; break;
1309 case 2: tap->wr_rate = 24; break;
1310 case 3: tap->wr_rate = 36; break;
1311 case 4: tap->wr_rate = 48; break;
1312 case 5: tap->wr_rate = 72; break;
1313 case 6: tap->wr_rate = 96; break;
1314 case 7: tap->wr_rate = 108; break;
1327 (void)ieee80211_input(ni, m, rssi - nf, nf);
1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
1334 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1351 struct ieee80211com *ic = &sc->sc_ic;
1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1356 if (ic->ic_dtim_count == 0)
1357 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1359 ic->ic_dtim_count--;
1365 if (ic->ic_dtim_count == 0)
1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1372 sc->sc_ic_flags = ic->ic_flags;
1380 struct ieee80211com *ic = &sc->sc_ic;
1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state));
1385 if (vap->iv_state == IEEE80211_S_RUN)
1452 struct ieee80211com *ic = &sc->sc_ic;
1453 struct ieee80211vap *vap = ni->ni_vap;
1459 const struct ieee80211_txparam *tp = ni->ni_txparms;
1470 data = SLIST_FIRST(&sc->data_pool);
1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1488 if (m->m_flags & M_EAPOL) {
1489 rate = tp->mgmtrate;
1490 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1491 rate = tp->mcastrate;
1492 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1493 rate = tp->ucastrate;
1496 rate = ni->ni_txrate;
1502 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1506 ring = &sc->txq[qid];
1507 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate);
1513 txwi = data->txwi;
1514 txwi->flags = 0;
1515 /* let HW generate seq numbers for non-QoS frames */
1516 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ;
1518 txwi->wcid = IEEE80211_AID(ni->ni_associd);
1520 txwi->wcid = 0xff;
1521 txwi->len = htole16(m->m_pkthdr.len);
1523 txwi->phy = htole16(RT2860_PHY_CCK);
1525 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1528 txwi->phy = htole16(RT2860_PHY_OFDM);
1529 txwi->phy |= htole16(mcs);
1532 * We store the MCS code into the driver-private PacketID field.
1539 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1541 /* check if RTS/CTS or CTS-to-self protection is required */
1542 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1543 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold ||
1544 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1546 txwi->txop = RT2860_TX_TXOP_HT;
1548 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1550 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1553 txwi->xflags |= RT2860_TX_ACK;
1555 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1559 *(uint16_t *)wh->i_dur = htole16(dur);
1564 txwi->flags |= RT2860_TX_TS;
1567 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1569 tap->wt_flags = 0;
1570 tap->wt_rate = rate;
1572 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1583 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1586 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1595 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1597 bus_dmamap_unload(sc->txwi_dmat, data->map);
1604 device_printf(sc->sc_dev,
1611 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1614 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1623 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1625 bus_dmamap_unload(sc->txwi_dmat, data->map);
1633 /* first segment is TXWI + 802.11 header */
1634 txd = &ring->txd[ring->cur];
1635 txd->sdp0 = htole32(data->paddr);
1636 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1637 txd->flags = qsel;
1641 for (i = nsegs; i >= 2; i -= 2) {
1642 txd->sdp1 = htole32(seg->ds_addr);
1643 txd->sdl1 = htole16(seg->ds_len);
1645 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1647 txd = &ring->txd[ring->cur];
1648 txd->sdp0 = htole32(seg->ds_addr);
1649 txd->sdl0 = htole16(seg->ds_len);
1650 txd->flags = qsel;
1653 /* finalize last segment */
1655 txd->sdp1 = htole32(seg->ds_addr);
1656 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1658 txd->sdl0 |= htole16(RT2860_TX_LS0);
1659 txd->sdl1 = 0;
1663 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1664 data->m = m;
1665 data->ni = ni;
1666 ring->data[ring->cur] = data;
1668 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1669 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1670 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1673 qid, txwi->wcid, nsegs, ridx));
1675 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1676 ring->queued += ntxds;
1677 if (ring->queued >= RT2860_TX_RING_COUNT)
1678 sc->qfullmsk |= 1 << qid;
1681 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1690 struct ieee80211com *ic = ni->ni_ic;
1691 struct rt2860_softc *sc = ic->ic_softc;
1697 if (!(sc->sc_flags & RT2860_RUNNING)) {
1715 sc->sc_tx_timer = 5;
1724 struct ieee80211com *ic = &sc->sc_ic;
1725 struct ieee80211vap *vap = ni->ni_vap;
1740 data = SLIST_FIRST(&sc->data_pool);
1746 rate = params->ibp_rate0;
1747 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
1749 if (ridx == (uint8_t)-1) {
1755 qid = params->ibp_pri & 3;
1756 ring = &sc->txq[qid];
1762 txwi = data->txwi;
1763 txwi->flags = 0;
1764 /* let HW generate seq numbers for non-QoS frames */
1765 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ;
1766 txwi->wcid = 0xff;
1767 txwi->len = htole16(m->m_pkthdr.len);
1769 txwi->phy = htole16(RT2860_PHY_CCK);
1771 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1774 txwi->phy = htole16(RT2860_PHY_OFDM);
1775 txwi->phy |= htole16(mcs);
1778 * We store the MCS code into the driver-private PacketID field.
1785 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1787 /* check if RTS/CTS or CTS-to-self protection is required */
1788 if (params->ibp_flags & IEEE80211_BPF_RTS ||
1789 params->ibp_flags & IEEE80211_BPF_CTS)
1790 txwi->txop = RT2860_TX_TXOP_HT;
1792 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1793 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
1794 txwi->xflags |= RT2860_TX_ACK;
1796 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1800 *(uint16_t *)wh->i_dur = htole16(dur);
1805 txwi->flags |= RT2860_TX_TS;
1808 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1810 tap->wt_flags = 0;
1811 tap->wt_rate = rate;
1813 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1824 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1827 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1836 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1838 bus_dmamap_unload(sc->txwi_dmat, data->map);
1845 device_printf(sc->sc_dev,
1852 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1855 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1864 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1866 bus_dmamap_unload(sc->txwi_dmat, data->map);
1874 /* first segment is TXWI + 802.11 header */
1875 txd = &ring->txd[ring->cur];
1876 txd->sdp0 = htole32(data->paddr);
1877 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1878 txd->flags = qsel;
1882 for (i = nsegs; i >= 2; i -= 2) {
1883 txd->sdp1 = htole32(seg->ds_addr);
1884 txd->sdl1 = htole16(seg->ds_len);
1886 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1888 txd = &ring->txd[ring->cur];
1889 txd->sdp0 = htole32(seg->ds_addr);
1890 txd->sdl0 = htole16(seg->ds_len);
1891 txd->flags = qsel;
1894 /* finalize last segment */
1896 txd->sdp1 = htole32(seg->ds_addr);
1897 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1899 txd->sdl0 |= htole16(RT2860_TX_LS0);
1900 txd->sdl1 = 0;
1904 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1905 data->m = m;
1906 data->ni = ni;
1907 ring->data[ring->cur] = data;
1909 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1910 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1911 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1914 qid, txwi->wcid, nsegs, ridx));
1916 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1917 ring->queued += ntxds;
1918 if (ring->queued >= RT2860_TX_RING_COUNT)
1919 sc->qfullmsk |= 1 << qid;
1922 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1930 struct rt2860_softc *sc = ic->ic_softc;
1934 if ((sc->sc_flags & RT2860_RUNNING) == 0) {
1938 error = mbufq_enqueue(&sc->sc_snd, m);
1957 if ((sc->sc_flags & RT2860_RUNNING) == 0)
1960 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 &&
1961 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1962 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1964 if_inc_counter(ni->ni_vap->iv_ifp,
1969 sc->sc_tx_timer = 5;
1980 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running"));
1982 if (sc->sc_invalid) /* card ejected */
1985 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1986 device_printf(sc->sc_dev, "device timeout\n");
1989 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1992 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
1998 struct rt2860_softc *sc = ic->ic_softc;
2002 if (ic->ic_nrunning> 0) {
2003 if (!(sc->sc_flags & RT2860_RUNNING)) {
2008 } else if (sc->sc_flags & RT2860_RUNNING)
2031 device_printf(sc->sc_dev,
2056 device_printf(sc->sc_dev,
2074 device_printf(sc->sc_dev, "could not read from BBP through MCU\n");
2080 * Write to one of the 4 programmable 24-bit RF registers.
2094 device_printf(sc->sc_dev, "could not write to RF\n");
2098 /* RF registers are 24-bit on the RT2860 */
2116 device_printf(sc->sc_dev, "could not read RF register\n");
2129 device_printf(sc->sc_dev, "could not read RF register\n");
2147 device_printf(sc->sc_dev, "could not write to RF\n");
2214 OFDM(6) << 28 | /* 54->48 */
2215 OFDM(5) << 24 | /* 48->36 */
2216 OFDM(4) << 20 | /* 36->24 */
2217 OFDM(3) << 16 | /* 24->18 */
2218 OFDM(2) << 12 | /* 18->12 */
2219 OFDM(1) << 8 | /* 12-> 9 */
2220 OFDM(0) << 4 | /* 9-> 6 */
2221 OFDM(0)); /* 6-> 6 */
2224 CCK(2) << 12 | /* 11->5.5 */
2225 CCK(1) << 8 | /* 5.5-> 2 */
2226 CCK(0) << 4 | /* 2-> 1 */
2227 CCK(0)); /* 1-> 1 */
2235 struct ieee80211com *ic = &sc->sc_ic;
2240 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2249 struct ieee80211com *ic = &sc->sc_ic;
2254 for (i = 0; i < rs->rs_nrates; i++) {
2255 rate = rs->rs_rates[i];
2260 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt,
2270 struct rt2860_softc *sc = ic->ic_softc;
2283 struct rt2860_softc *sc = ic->ic_softc;
2284 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2286 if (vap->iv_state == IEEE80211_S_RUN) {
2296 struct rt2860_softc *sc = ic->ic_softc;
2304 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) {
2314 struct rt2860_softc *sc = ic->ic_softc;
2317 rt2860_switch_chan(sc, ic->ic_curchan);
2327 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2328 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2329 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2333 if (sc->ext_2ghz_lna) {
2341 if (sc->ext_5ghz_lna) {
2357 if (sc->nrxchains > 1)
2359 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2363 if (sc->ntxchains > 1)
2365 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2369 if (sc->ntxchains > 1)
2371 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2376 if (sc->mac_ver == 0x3593) {
2378 if (sc->sc_flags & RT2860_PCIE) {
2393 if (sc->mac_ver >= 0x3071)
2394 agc = 0x1c + sc->lna[0] * 2;
2396 agc = 0x2e + sc->lna[0];
2398 agc = 0x32 + (sc->lna[group] * 5) / 3;
2417 if (sc->ntxchains == 1)
2419 if (sc->nrxchains == 1)
2421 else if (sc->nrxchains == 2)
2425 txpow1 = sc->txpow1[i];
2426 txpow2 = sc->txpow2[i];
2431 txpow1 = (7 + txpow1) << 1;
2435 txpow2 = (7 + txpow2) << 1;
2437 r3 = rfprog[i].r3 | txpow1 << 7;
2438 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2474 txpow1 = sc->txpow1[i];
2475 txpow2 = sc->txpow2[i];
2497 if (sc->ntxchains == 1)
2499 else if (sc->ntxchains == 2)
2501 if (sc->nrxchains == 1)
2503 else if (sc->nrxchains == 2)
2509 rf = (rf & ~0x7f) | sc->freq;
2514 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2517 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2521 rf = rt3090_rf_read(sc, 7);
2522 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2539 txpow1 = sc->txpow1[i];
2540 txpow2 = sc->txpow2[i];
2554 if (sc->mac_ver == 0x5392) {
2565 if (sc->mac_ver == 0x5392)
2576 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2581 if (sc->mac_ver == 0x5390) {
2586 else if (chan >= 7 && chan <= 10)
2600 else if (chan >= 7 && chan <= 12)
2610 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2634 /* toggle RF R30 bit 7 */
2641 if (sc->patch_dac && sc->mac_rev < 0x0211)
2663 if (sc->mac_ver != 0x3593) {
2665 sc->rf24_20mhz = 0x1f; /* default value */
2666 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2675 sc->rf24_40mhz = 0x2f; /* default value */
2676 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2682 if (sc->mac_rev < 0x0211)
2688 if (sc->rf_rev == RT3070_RF_3020)
2692 if (sc->mac_ver == 0x3593) {
2693 if (sc->ntxchains == 1)
2695 else if (sc->ntxchains == 2)
2697 if (sc->nrxchains == 1)
2699 else if (sc->nrxchains == 2)
2702 if (sc->ntxchains == 1)
2704 if (sc->nrxchains == 1)
2719 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2721 if (sc->txmixgain_2ghz >= 2)
2722 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2741 /* Toggle RF R2 bit 7. */
2747 if (sc->mac_ver == 0x5392) {
2759 sc->rf24_20mhz = 0x1f;
2760 sc->rf24_40mhz = 0x2f;
2762 if (sc->mac_rev < 0x0211)
2771 if (sc->mac_ver == 0x5390)
2780 if (sc->mac_rev >= 0x0211)
2784 if (sc->ntxchains == 1)
2786 if (sc->nrxchains == 1)
2809 if (sc->mac_ver == 0x3593) {
2845 rf = rt3090_rf_read(sc, 7);
2846 rt3090_rf_write(sc, 7, rf | 0x30);
2858 if (sc->mac_rev < 0x0211)
2862 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2878 if (sc->mac_ver == 0x5392)
2884 if (sc->mac_ver == 0x5390)
2898 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2945 delta = bbp55_pb - bbp55_sb;
2955 rf24--; /* backtrack */
2976 if (sc->mac_rev >= 0x0211) {
2986 if (sc->mac_rev < 0x0211) {
2988 sc->patch_dac ? 0x2c : 0x0f);
2993 if (sc->mac_ver < 0x5390) {
2995 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
2997 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
3006 which | (sc->leds & 0x7f), 0);
3010 * Hardware has a general-purpose programmable timer interrupt that can
3056 struct rt2860_softc *sc = ic->ic_softc;
3068 struct ieee80211com *ic = &sc->sc_ic;
3073 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
3080 if (ic->ic_flags & IEEE80211_F_USEPROT) {
3081 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3083 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3092 struct rt2860_softc *sc = ic->ic_softc;
3097 if (ic->ic_promisc == 0)
3105 struct rt2860_softc *sc = ic->ic_softc;
3154 struct rt2860_softc *sc = ic->ic_softc;
3160 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
3165 switch (k->k_cipher) {
3182 if (k->k_flags & IEEE80211_KEY_GROUP) {
3184 base = RT2860_SKEY(0, k->k_id);
3186 wcid = ((struct rt2860_node *)ni)->wcid;
3190 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3191 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3193 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3194 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3195 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3199 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3200 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3203 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3205 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3206 (k->k_flags & IEEE80211_KEY_TX)) {
3208 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3209 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3217 iv[3] = k->k_id << 6;
3218 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3220 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3221 iv[0] = k->k_tsc >> 8;
3223 iv[2] = k->k_tsc;
3225 iv[0] = k->k_tsc;
3226 iv[1] = k->k_tsc >> 8;
3229 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3230 iv[4] = k->k_tsc >> 16;
3231 iv[5] = k->k_tsc >> 24;
3232 iv[6] = k->k_tsc >> 32;
3233 iv[7] = k->k_tsc >> 40;
3238 if (k->k_flags & IEEE80211_KEY_GROUP) {
3241 attr &= ~(0xf << (k->k_id * 4));
3242 attr |= mode << (k->k_id * 4);
3257 struct rt2860_softc *sc = ic->ic_softc;
3261 if (k->k_flags & IEEE80211_KEY_GROUP) {
3264 attr &= ~(0xf << (k->k_id * 4));
3269 wcid = ((struct rt2860_node *)ni)->wcid;
3280 struct ieee80211com *ic = &sc->sc_ic;
3281 struct ieee80211_channel *c = ic->ic_curchan;
3286 delta = sc->rssi_5ghz[rxchain];
3290 delta -= sc->lna[1];
3292 delta -= sc->lna[2];
3294 delta -= sc->lna[3];
3296 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3298 return -12 - delta - rssi;
3302 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3303 * Used to adjust per-rate Tx power registers.
3352 sc->sc_srom_read = rt2860_eeprom_read_2;
3353 if (sc->mac_ver >= 0x3071) {
3357 sc->sc_srom_read = rt3090_efuse_read_2;
3386 sc->bbp[i].val = val & 0xff;
3387 sc->bbp[i].reg = val >> 8;
3388 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3390 if (sc->mac_ver >= 0x3071) {
3394 sc->rf[i].val = val & 0xff;
3395 sc->rf[i].reg = val >> 8;
3396 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3397 sc->rf[i].val));
3403 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3404 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3407 sc->leds = val >> 8;
3408 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3409 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3410 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3413 sc->leds = 0x01;
3414 sc->led[0] = 0x5555;
3415 sc->led[1] = 0x2221;
3416 sc->led[2] = 0xa9f8;
3419 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3423 if (sc->mac_ver >= 0x5390)
3424 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID);
3426 sc->rf_rev = (val >> 8) & 0xf;
3427 sc->ntxchains = (val >> 4) & 0xf;
3428 sc->nrxchains = val & 0xf;
3430 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3437 sc->patch_dac = (val >> 15) & 1;
3439 sc->ext_5ghz_lna = (val >> 3) & 1;
3440 sc->ext_2ghz_lna = (val >> 2) & 1;
3442 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */
3444 sc->rfswitch = val & 1;
3446 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3450 sc->pslevel = val & 0x3;
3453 sc->pslevel = MIN(sc->pslevel, 1);
3454 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3462 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3463 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3465 if (sc->mac_ver != 0x5390) {
3468 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3469 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3474 if (sc->txpow1[i] < 0 ||
3475 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3476 sc->txpow1[i] = 5;
3477 if (sc->mac_ver != 0x5390) {
3478 if (sc->txpow2[i] < 0 ||
3479 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3480 sc->txpow2[i] = 5;
3483 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3489 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3490 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3494 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3495 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3499 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3500 sc->txpow1[14 + i] = 5;
3501 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3502 sc->txpow2[14 + i] = 5;
3504 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3505 sc->txpow2[14 + i]));
3514 delta_2ghz = -delta_2ghz;
3520 delta_5ghz = -delta_5ghz;
3533 sc->txpow20mhz[ridx] = reg;
3534 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3535 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3538 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3539 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3542 /* read factory-calibrated samples for temperature compensation */
3544 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3545 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3547 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3548 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3550 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3551 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3553 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3554 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3556 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3557 sc->step_2ghz = val >> 8;
3559 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3560 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3561 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3562 sc->tssi_2ghz[8], sc->step_2ghz));
3564 if (sc->tssi_2ghz[4] == 0xff)
3565 sc->calib_2ghz = 0;
3568 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3569 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3571 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3572 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3574 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3575 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3577 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3578 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3580 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3581 sc->step_5ghz = val >> 8;
3583 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3584 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3585 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3586 sc->tssi_5ghz[8], sc->step_5ghz));
3588 if (sc->tssi_5ghz[4] == 0xff)
3589 sc->calib_5ghz = 0;
3593 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3594 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3596 if (sc->mac_ver >= 0x3071) {
3602 sc->txmixgain_2ghz = val & 0x7;
3603 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3605 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3606 sc->lna[2] = val >> 8; /* channel group 2 */
3609 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3610 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3612 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3613 sc->lna[3] = val >> 8; /* channel group 3 */
3616 if (sc->mac_ver >= 0x3071)
3617 sc->lna[0] = RT3090_DEF_LNA;
3619 sc->lna[0] = val & 0xff;
3620 sc->lna[1] = val >> 8; /* channel group 1 */
3623 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3625 sc->lna[2] = sc->lna[1];
3627 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3629 sc->lna[3] = sc->lna[1];
3634 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3636 ant + 1, sc->rssi_2ghz[ant]));
3637 sc->rssi_2ghz[ant] = 0;
3639 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3641 ant + 1, sc->rssi_5ghz[ant]));
3642 sc->rssi_5ghz[ant] = 0;
3661 device_printf(sc->sc_dev,
3667 if (sc->mac_ver >= 0x5390)
3677 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3680 if (sc->mac_ver >= 0x3071) {
3684 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3699 if (sc->nrxchains > 1) {
3713 if (sc->mac_ver == 0x5392) {
3726 if (sc->mac_ver == 0x5390)
3733 struct ieee80211com *ic = &sc->sc_ic;
3747 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3759 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3764 if (ic->ic_opmode == IEEE80211_M_STA)
3779 struct ieee80211com *ic = &sc->sc_ic;
3785 if (sc->sc_flags & RT2860_RUNNING)
3792 struct ieee80211com *ic = &sc->sc_ic;
3793 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3800 if (sc->rfswitch) {
3801 /* hardware has a radio switch on GPIO pin 2 */
3803 device_printf(sc->sc_dev,
3831 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
3836 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
3840 if (sc->txpow20mhz[ridx] == 0xffffffff)
3842 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3852 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3877 if (sc->mac_ver >= 0x5390)
3879 else if (sc->mac_ver >= 0x3071) {
3886 sc->sc_flags |= RT2860_PCIE;
3901 device_printf(sc->sc_dev, "timeout waiting for MAC\n");
3933 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
3939 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
3941 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
3945 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
3954 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3966 /* write vendor-specific BBP values (from EEPROM) */
3968 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
3970 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
3974 if (sc->rf_rev == RT3070_RF_2020 ||
3975 sc->rf_rev == RT3070_RF_3020 ||
3976 sc->rf_rev == RT3070_RF_3320 ||
3977 sc->mac_ver == 0x5390)
3981 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
3982 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
3983 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
3985 if (sc->mac_ver >= 0x5390)
3987 else if (sc->mac_ver >= 0x3071) {
3997 if (sc->mac_ver >= 0x5390)
3999 else if (sc->mac_ver >= 0x3071)
4002 /* disable non-existing Rx chains */
4005 if (sc->nrxchains == 2)
4007 else if (sc->nrxchains == 3)
4011 /* disable non-existing Tx chains */
4013 if (sc->ntxchains == 1)
4015 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
4017 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
4021 if (sc->mac_ver >= 0x3071)
4025 rt2860_switch_chan(sc, ic->ic_curchan);
4053 if (sc->sc_flags & RT2860_ADVANCED_PS)
4054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
4056 sc->sc_flags |= RT2860_RUNNING;
4058 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
4077 if (sc->sc_flags & RT2860_RUNNING)
4080 callout_stop(&sc->watchdog_ch);
4081 sc->sc_tx_timer = 0;
4082 sc->sc_flags &= ~RT2860_RUNNING;
4101 sc->qfullmsk = 0;
4103 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
4104 rt2860_reset_rx_ring(sc, &sc->rxq);
4119 device_printf(sc->sc_dev,
4127 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize);
4144 device_printf(sc->sc_dev,
4162 struct ieee80211com *ic = &sc->sc_ic;
4170 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4171 tssi = &sc->tssi_2ghz[4];
4172 step = sc->step_2ghz;
4174 tssi = &sc->tssi_5ghz[4];
4175 step = sc->step_5ghz;
4180 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4194 if (sc->txpow20mhz[ridx] == 0xffffffff)
4197 b4inc(sc->txpow20mhz[ridx], d));
4208 if (sc->mac_ver == 0x5390) {
4218 if (sc->mac_ver == 0x5390) {
4233 struct ieee80211com *ic = &sc->sc_ic;
4240 if (sc->mac_ver >= 0x5390)
4242 else if (sc->mac_ver >= 0x3071)
4258 if (sc->mac_ver < 0x5390)
4267 struct ieee80211com *ic = vap->iv_ic;
4272 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL)
4277 txwi.len = htole16(m->m_pkthdr.len);
4279 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ?
4291 mtod(m, uint8_t *), m->m_pkthdr.len);
4301 struct ieee80211com *ic = &sc->sc_ic;
4302 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4308 tmp |= vap->iv_bss->ni_intval * 16;
4310 if (vap->iv_opmode == IEEE80211_M_STA) {
4317 else if (vap->iv_opmode == IEEE80211_M_IBSS ||
4318 vap->iv_opmode == IEEE80211_M_MBSS) {
4325 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {