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/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Dfsl-qdma.txt8 - compatible: Must be one of
9 "fsl,ls1021a-qdma": for LS1021A Board
10 "fsl,ls1028a-qdma": for LS1028A Board
11 "fsl,ls1043a-qdma": for ls1043A Board
12 "fsl,ls1046a-qdma": for ls1046A Board
13 - reg: Should contain the register's base address and length.
14 - interrupts: Should contain a reference to the interrupt used by this
16 - interrupt-names: Should contain interrupt names:
17 "qdma-queue0": the block0 interrupt
18 "qdma-queue1": the block1 interrupt
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-binding
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H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controlle
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H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gi
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/freebsd-src/sys/contrib/device-tree/Bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cell
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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dgeneric-ohci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 - items:
16 - enum:
17 - allwinner,sun4i-a10-ohci
18 - allwinner,sun50i-a64-ohci
19 - allwinner,sun50i-h6-ohci
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H A Dgeneric-ehci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartma
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/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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/freebsd-src/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_ppc64.S19 stdu r1,-48(r1)
26 ld r4,-28696(r13)
29 // For big-endian, we load the TOC from the OPD. For little-
30 // endian, we use the .TOC. symbol to find it.
36 addis r2,r2,.TOC.-0b@ha
37 addi r2,r2,.TOC.-0b@l
39 addis r2,r2,_setjmp-0b@ha
40 addi r2,r2,_setjmp-0b@l
46 // Restore regs needed for setjmp.
54 ld r6,-28696(r13)
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/freebsd-src/sys/dev/enetc/
H A Denetc_hw.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
11 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
23 /** SI regs, offset: 0h */
52 /* VF-PF Message passing */
81 /* Control BDR regs */
111 /** SI BDR sub-blocks, n = 0..7 */
163 /* Port regs, offset: 1_0000h */
340 /** Global regs, offset: 2_0000h */
448 uint32_t sip_h[4]; /* Big-endian */
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/freebsd-src/contrib/arm-optimized-routines/string/aarch64/
H A Dstrncmp.S2 * strncmp - compare two strings
4 * Copyright (c) 2013-2022, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
10 * ARMv8-a, AArch64.
44 /* Define endian dependent shift operations.
45 On big-endia
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/freebsd-src/sys/arm64/arm64/
H A Dstrncmp.S2 * strncmp - compare two strings
4 * Copyright (c) 2013-2022, Arm Limited.
5 * SPDX-License-Identifier: MIT
10 * ARMv8-a, AArch64.
48 /* Define endian dependent shift operations.
49 On big-endian early bytes are at MSB and on little-endian LSB.
70 /* NUL detection works on the principle that (X - 1) & (~X) & 0x80
71 (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
81 eor diff, data1, data2 /* Non-zero if differences found. */
83 bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
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/freebsd-src/contrib/file/magic/Magdir/
H A Dhp2 #----------
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/freebsd-src/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
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H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------
1340 createARMAsmBackend(const Target & T,const MCSubtargetInfo & STI,const MCRegisterInfo & MRI,const MCTargetOptions & Options,llvm::endianness Endian) createARMAsmBackend() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -------
344 buildCopyFromRegs(MachineIRBuilder & B,ArrayRef<Register> OrigRegs,ArrayRef<Register> Regs,LLT LLTy,LLT PartLLT,const ISD::ArgFlagsTy Flags) buildCopyFromRegs() argument
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h1 //===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===//
5 // SPDX-License-Identifie
63 SmallVector<Register, 4> Regs; global() member
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/freebsd-src/contrib/ntp/ntpd/
H A Drefclock_gpsvme.c1 /* refclock_psc.c: clock driver for Brandywine PCI-SyncClock32/HP-UX 11.X */
67 #define PRECISION (-20) /* precision assumed (1 us) */
69 #define DESCRIPTION "Brandywine PCI-SyncClock32"
116 /* get the address of the mapped regs */ in psc_start()
123 pp = peer->procptr; in psc_start()
124 pp->io.clock_recv = noentry; in psc_start()
125 pp->io.srcclock = peer; in psc_start()
126 pp->io.datalen = 0; in psc_start()
127 pp->io.fd = -1; in psc_start()
128 pp->unitptr = up; in psc_start()
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/freebsd-src/sys/dev/e1000/
H A De1000_82542.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
55 * e1000_init_phy_params_82542 - Init PHY func ptrs.
60 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82542()
65 phy->type = e1000_phy_none; in e1000_init_phy_params_82542()
71 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
76 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_82542()
80 nvm->address_bits = 6; in e1000_init_nvm_params_82542()
81 nvm->delay_usec = 50; in e1000_init_nvm_params_82542()
82 nvm->opcode_bits = 3; in e1000_init_nvm_params_82542()
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/freebsd-src/usr.sbin/bhyve/
H A Dgdb.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2017-2018 John H. Baldwin <jhb@FreeBSD.org>
32 #include <sys/endian.h>
109 static int xml_dfd = -1;
159 static int cur_fd = -1;
268 if (caph_limit_stream(fileno(logfile), CAPH_WRITE) == - in debug()
290 uint64_t regs[4]; guest_paging_info() local
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/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exceptio
219 const CodeGenRegister::Vec &Regs = RC.getMembers(); EmitRegUnitPressure() local
384 EmitRegMappingTables(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor) EmitRegMappingTables() argument
511 EmitRegMapping(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor) EmitRegMapping() argument
878 const auto &Regs = RegBank.getRegisters(); runMCDesc() local
1442 const auto &Regs = RegBank.getRegisters(); runTargetDesc() local
1679 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); runTargetDesc() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface -------
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