Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
49 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");
52 RegisterInfoDebug("register-info-debug", cl::init(false),
68 // runEnums - Print out enum values for all of the registers.
71 // runMCDesc - Print out MC register descriptions.
74 // runTargetHeader - Emit a header fragment for the register info emitter.
78 // runTargetDesc - Output the target register and register file descriptions.
82 // run - Output the register file description.
88 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
91 const std::deque<CodeGenRegister> &Regs,
103 // runEnums - Print out enum values for all of the registers.
109 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
111 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
165 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
218 const CodeGenRegister::Vec &Regs = RC.getMembers();
220 if (Regs.empty() || RC.Artificial)
230 << " return RCWeightTable[RC->getID()];\n"
318 PSetsSeqs.emit(OS, printInt, "-1");
323 << "/// Returns a -1 terminated array of pressure set IDs\n"
326 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
332 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
337 << "/// Returns a -1 terminated array of pressure set IDs\n"
342 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
358 // Sort and unique to get a map-like vector. We want the last assignment to
367 if (LastSeenReg && Reg->getName() == LastSeenReg->getName())
368 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
375 return A.first->getName() == B.first->getName();
381 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
387 for (auto &RE : Regs) {
389 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
398 // Now we know maximal length of number list. Append -1's, where needed
401 DwarfRegNum.second.push_back(-1);
403 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
405 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
448 for (auto &RE : Regs) {
450 const RecordVal *V = Reg->getValue("DwarfAlias");
451 if (!V || !V->getValue())
454 DefInit *DI = cast<DefInit>(V->getValue());
455 Record *Alias = DI->getDef();
460 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias &&
466 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg &&
468 RegIter->second = AliasIter->second;
483 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
508 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
512 for (auto &RE : Regs) {
515 Reg->getValueAsListOfInts("DwarfNumbers").size());
521 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
538 OS << "RI->";
569 OS << "RI->";
586 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
619 OS << Idx->EnumValue;
642 V.push_back(Cur - Val);
653 unsigned Cur = (*I)->EnumValue;
654 V.push_back(Cur - Val);
670 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
672 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
679 auto *&Entry = Vec[I.first->EnumValue - 1];
693 // Many sub-register indexes are composition-compatible, meaning that
697 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
700 // Map each Sub-register index to a compatible table row.
739 OS << Rows[r][i]->getQualifiedName() << ", ";
746 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n"
747 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
822 " --IdxA; assert(IdxA < "
828 " Ops->Mask.any(); ++Ops) {\n"
830 "Ops->Mask.getAsInteger();\n"
831 " if (unsigned S = Ops->RotateLeft)\n"
832 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - "
844 " --IdxA; assert(IdxA < "
850 " Ops->Mask.any(); ++Ops) {\n"
852 " if (unsigned S = Ops->RotateLeft)\n"
853 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - "
863 // runMCDesc - Print out MC register descriptions.
872 const auto &Regs = RegBank.getRegisters();
875 // The lists of sub-registers and super-registers go in the same array. That
881 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
882 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
883 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
887 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
889 // Keep track of sub-register names as well. These are not differentially
893 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
899 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
903 // Compute the ordered sub-register list.
909 // Compute the corresponding sub-register indexes.
915 // Super-registers are already computed.
952 // Emit the table of sub-register indexes.
968 for (const auto &Reg : Regs) {
974 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big");
995 OS << LS << getQualifiedName(R->TheDef);
1016 // Emit the register list now (unless it would be a zero-length array).
1029 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1063 EmitRegMappingTables(OS, Regs, false);
1070 for (const auto &RE : Regs) {
1072 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
1074 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
1075 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
1076 Value |= (uint64_t)B->getValue() << b;
1087 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
1088 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1096 EmitRegMapping(OS, Regs, false);
1187 // runTargetDesc - Output the target register and register file descriptions.
1245 // Emit the table of sub-register index sizes.
1249 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
1302 // register class, RC, is the set of sub-classes, including RC itself.
1304 // If RC has super-registers, also create a list of subreg indices and bit
1310 // The 0-terminated list of subreg indices starts at:
1312 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1314 // The corresponding bitmasks follow the sub-class mask in memory. Each
1319 // Compress the sub-reg index lists.
1330 // Emit super-reg class masks for any relevant SubRegIndices that can
1352 // Emit NULL terminated super-class lists.
1363 OS << " &" << Super->getQualifiedName() << "RegClass,\n";
1399 // Now emit the actual value-initialized register class instances.
1440 const auto &Regs = RegBank.getRegisters();
1442 for (const auto &Reg : Regs)
1446 llvm::BitVector InAllocClass(Regs.size() + 1, false);
1452 for (const auto &Reg : Regs) {
1457 NumRegCosts - Costs.size(), 0);
1463 // Emit the cost values as a 1D-array after grouping them by their indices,
1465 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1).
1515 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1516 << " -> " << SRC->getName() << "\n";
1523 << " if (!Idx) return RC;\n --Idx;\n"
1525 << " unsigned TV = Table[RC->getID()][Idx];\n"
1526 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1552 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;
1553 EnumValue = SubRegClass->EnumValue + 1;
1560 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;
1561 OS << " -> " << SubRegClass->getName();
1570 << " if (!Idx) return RC;\n --Idx;\n"
1572 << " unsigned TV = Table[RC->getID()][Idx];\n"
1573 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1594 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) <
1595 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue);
1606 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";
1608 for (const CodeGenRegister &Reg : Regs) {
1611 if (is_contained(RC->getMembers(), &Reg)) {
1618 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID")
1641 EmitRegMappingTables(OS, Regs, true);
1654 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1667 EmitRegMapping(OS, Regs, true);
1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1677 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1679 // Emit the *_SaveList list of callee-saved registers.
1680 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { ";
1681 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1682 OS << getQualifiedName((*Regs)[r]) << ", ";
1685 // Emit the *_RegMask bit mask of call-preserved registers.
1686 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1691 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1693 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1707 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { ";
1718 OS << " " << CSRSet->getName() << "_RegMask,\n";
1735 OS << " " << RC->getQualifiedName()
1749 OS << " " << RC->getQualifiedName()
1763 OS << " " << RC->getQualifiedName()
1773 for (const auto &Reg : Regs)
1784 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";
1825 auto getModeName = [CGH](unsigned M) -> StringRef {
1848 OS << " " << R->getName();
1861 OS << " " << SRC->getName();
1889 OS << "\tSubReg " << P.first->getName() << " = " << P.second->getName()
1896 X("gen-register-info", "Generate registers and register classes info");