Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
29 #define DEBUG_TYPE "call-lowering"
108 .getFnAttribute("disable-tail-calls")
113 bool IsVarArg = CB.getFunctionType()->isVarArg();
125 // The sret demotion isn't compatible with tail-calls, since the sret
134 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
141 // might point to function-local memory), we can't meaningfully tail-call.
151 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
156 CalleeV = cast<ConstantPtrAuth>(CalleeV)->getPointer();
161 if (F->hasFnAttribute(Attribute::NonLazyBind)) {
162 LLT Ty = getLLTForType(*F->getType(), DL);
170 // callee must be in the same TU and therefore we can direct-call it without
181 if (!Info.OrigRet.Ty->isVoidTy()) {
187 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
195 Info.CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
196 assert(Info.CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
227 PointerType *PtrTy = dyn_cast<PointerType>(Arg.Ty->getScalarType());
230 Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace());
237 unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
262 MemAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
265 FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
292 LLVMContext &Ctx = OrigArg.Ty->getContext();
302 // double] -> double).
303 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
310 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
312 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
316 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,
350 // promoted to a vector e.g. s8 -> v4s8 -> s8
371 /// value registers of type \p LLTy, and \p Regs contains the legalized pieces
374 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
381 assert(OrigRegs[0] == Regs[0]);
386 Regs.size() == 1) {
387 B.buildBitcast(OrigRegs[0], Regs[0]);
397 OrigRegs.size() == 1 && Regs.size() == 1) {
398 Register SrcReg = Regs[0];
426 unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
428 B.buildMergeValues(OrigRegs[0], Regs);
430 auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs);
439 SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
447 Regs.size() == 1) {
450 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
485 for (Register Reg : Regs)
489 B.buildBuildVector(OrigRegs[0], Regs);
491 // Deal with vector with 64-bit elements decomposed to 32-bit
492 // registers. Need to create intermediate 64-bit elements.
500 B.buildMergeLikeInstr(ExtendedPartTy, Regs.take_front(PartsPerElt));
506 Regs = Regs.drop_front(PartsPerElt);
517 if (NumElts == Regs.size())
518 BuildVec = B.buildBuildVector(BVType, Regs).getReg(0);
521 // e.g. we have a <4 x s16> but 2 x s32 in regs.
522 assert(NumElts > Regs.size());
523 LLT SrcEltTy = MRI.getType(Regs[0]);
534 BVRegs.reserve(Regs.size() * EltPerReg);
535 for (Register R : Regs) {
544 assert((BVRegs.size() - NumElts) < EltPerReg);
586 // A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
684 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT);
686 // If we need to split the type over multiple regs, check it's a scenario
689 TLI->getNumRegistersForCallingConv(Ctx, CallConv, CurVT);
702 // multiple regs, so we have to record this information for later.
708 // We're handling an incoming arg which is split over multiple regs.
719 if (Part == NumParts - 1)
775 j += (NumArgRegs - 1);
792 // Expected to be multiple regs for a single incoming arg.
793 // There should be Regs.size() ArgLocs per argument.
798 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
803 Args[i].Regs.resize(NumParts);
809 Args[i].Regs[0] = MRI.createGenericVirtualRegister(PointerTy);
815 Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
819 assert((j + (NumParts - 1)) < ArgLocs.size() &&
820 "Too many regs for number of args");
826 buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
831 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
836 Register ArgReg = Args[i].Regs[Part];
837 // There should be Regs.size() ArgLocs per argument.
838 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
880 // store. We may need to adjust the offset for big endian targets.
900 assert(Args[i].Regs.size() == 1 && "didn't expect split byval pointer");
907 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
933 Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
961 MIRBuilder.buildLoad(Args[i].OrigRegs[0], Args[i].Regs[0], MPO,
971 // Now that all pieces have been assigned, re-pack the register typed values
978 buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
982 j += NumParts - 1;
1006 PointerType::get(RetTy->getContext(), DL.getAllocaAddrSpace());
1037 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getPointerTo(AS)), DL);
1066 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()),
1110 LLVMContext &Context = RetTy->getContext();
1119 TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
1120 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
1152 // Only look at callee-saved registers.
1158 << "... Call has an argument passed in a callee-saved register.\n");
1163 if (OutInfo.Regs.size() > 1) {
1172 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
1173 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
1181 Register CopyRHS = RegDef->getOperand(1).getReg();
1183 LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
1309 // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1321 // nop in big-endian situations.