Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
51 /// FSEL - Traditional three-operand fsel node.
55 /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
59 /// FCFID - The FCFID instruction, taking an f64 operand and producing
64 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
65 /// unsigned integers and single-precision outputs.
70 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
76 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
81 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
82 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
95 /// VPERM - The PPC VPERM Instruction.
99 /// XXSPLT - The PPC VSX splat instructions
103 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
108 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
112 /// VECINSERT - The PPC vector insert instruction
116 /// VECSHL - The PPC vector shift left instruction
120 /// XXPERMDI - The PPC XXPERMDI instruction
128 /// Hi/Lo - These represent the high and low 16-bit parts of a global
136 /// The following two target-specific nodes are used for calls through
137 /// function pointers in the 64-bit SVR4 ABI.
167 /// FNMSUB - Negated multiply-subtract instruction.
170 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
180 /// CALL - A direct function call.
181 /// CALL_NOP is a call with the special NOP which follows 64-bit
183 /// SVR4 calls and 32-bit/64-bit AIX calls.
188 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
192 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
196 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
197 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
198 /// and 64-bit AIX.
212 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
214 /// resultant GPR. Bits corresponding to other CR regs are undefined.
241 /// For example v2i32 -> widened to v4i32 -> v2f64
257 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
263 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
267 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
270 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
273 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
279 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
285 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
292 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
297 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
298 /// towards zero. Used only as part of the long double-to-int
302 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
305 /// TC_RETURN - A tail call return.
312 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
316 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
317 /// for non-position independent code on PPC32.
324 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
329 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
335 /// G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec
336 /// and local-exec TLS models, produces an ADD instruction that adds
343 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
348 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
354 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
359 /// %x3 = GET_TPOINTER - Used for the local- and initial-exec TLS model on
360 /// 32-bit AIX, produces a call to .__get_tpointer to retrieve the thread
364 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
374 /// This node is used in 64-bit mode as well (in which case the result is
378 /// %x3 = GET_TLS_MOD_AIX _$TLSML - For the AIX local-dynamic TLS model,
385 /// to .__tls_get_mod. This node is used in both 32-bit and 64-bit modes.
389 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
394 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
400 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
405 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
410 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
415 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
420 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS
424 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
430 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
434 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
437 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
441 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
444 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
445 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
455 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
495 /// Constrained integer-to-floating-point conversion instructions.
501 /// Constrained floating point add in round-to-zero mode.
504 // NOTE: The nodes below may require PC-Rel specific patterns if the
505 // address could be PC-Relative. When adding new nodes below, consider
506 // whether or not the address can be PC-Relative and add the corresponding
507 // PC-relative patterns and tests.
509 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
510 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
515 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
516 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
521 /// STFIWX - The STFIWX instruction. The first operand is an input token
525 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
526 /// load which sign-extends from a 32-bit integer value into the
527 /// destination 64-bit register.
530 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
531 /// load which zero-extends from a 32-bit integer value into the
532 /// destination 64-bit register.
535 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
536 /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
540 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
542 /// followed by a byte-width for the store.
545 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
550 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend
556 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
558 /// the vector type to load vector in big-endian element order.
561 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
565 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
569 /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
570 /// that zero-extends.
573 /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory
574 /// that sign-extends.
577 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
582 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
584 /// the vector type to store vector in big-endian element order.
590 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
591 /// except they ensure that the compare input is zero-extended for
592 /// sub-word versions because the atomic loads zero-extend.
612 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
617 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
622 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
627 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
632 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
637 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
641 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
646 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
650 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
654 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
658 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
662 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
667 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
668 /// shift amount, otherwise return -1.
672 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
677 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
687 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
688 /// appropriate for PPC mnemonics (which have a big endian bias - namely
693 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
696 /// the number of bytes of each element [124] -> [bhw].
710 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant.
711 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation
712 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4.
713 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16.
714 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant.
716 MOF_PCRel = 1 << 12, // PC-Relative relocation.
717 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant.
719 // The in-memory type.
753 /// getTargetNodeName() - This method returns the name of a target specific
762 /// getPreferredVectorAction - The code we generate when vector types are
772 // Default handling for scalable and single-element vectors.
832 /// getSetCCResultType - Return the ISD::SETCC ValueType
841 /// getPreIndexedAddressParts - returns true by value, base pointer and
843 /// can be legally represented as pre-indexed load / store address.
849 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
854 /// SelectAddressRegReg - Given the specified addressed, check to see if it
856 /// is non-zero, only accept displacement which is not suitable for [r+imm].
862 /// SelectAddressRegImm - Returns true if the address N can be represented
863 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
865 /// non-zero, only accept displacements suitable for instruction encoding
873 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
878 /// SelectAddressPCRel - Represent the specified address as pc relative to
884 /// LowerOperation - Provide custom lowering hooks for some operations.
888 /// ReplaceNodeResults - Replace the results of node with an illegal result
981 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
987 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1010 /// isLegalAddressingMode - Return true if the addressing mode represented
1016 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1022 /// isLegalAddImmediate - Return true if the specified immediate is legal
1028 /// isTruncateFree - Return true if it's free to truncate a value of
1030 /// register X1 to i32 by referencing its sub-register R1.
1073 /// target-independent logic.
1084 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
1093 /// isProfitableToHoist - Check if it is profitable to hoist instruction
1106 // Keep the zero-extensions for arguments to libcalls.
1109 /// createFastISel - This method returns a target-specific FastISel object,
1126 return Ty->isArrayTy();
1155 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode),
1162 /// SelectForceXFormMode - Given the specified address, force it to be
1441 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1461 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1467 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1472 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1482 /// getAddrModeForFlags - Based on the set of address flags, select the most
1486 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute