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/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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/freebsd-src/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IS
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H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPU
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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controlle
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/Support/
H A DRISCVISAInfo.h
H A DRISCVAttributes.h1 //===-- RISCVAttributes.h - RISCV Attributes -------
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/freebsd-src/share/i18n/csmapper/MISC/
H A DRISCOS-LATIN1%UCS.src1 # $NetBSD: RISCOS-LATIN1%UCS.src,v 1.1 2007/04/01 18:52:29 tnozaki Exp $
4 NAME "RISCOS-LATIN1/UCS"
5 SRC_ZONE 0x00-0xFF
12 # Id: RISCOS.TXT,v 1.1 2003/05/19 20:26:32 mleisher Exp
14 # The charset used on RISC OS ('Acorn RISC OS'). The same as Latin-1,
17 # -- Ed Avis, <ed@membled.com>, 2001-03-08
19 # First everything from Latin-1 outside 0x80 -| 0xA0.
20 # Now the RISC OS specific characters. This is from RISC OS 3.11. In
21 # earlier versions of RISC OS, some of these were used for drawing
27 # in Homerton, one of the outline fonts that comes with RISC OS. The
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h1 //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions ----
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCV.td1 //===-- RISCV.td - Describe the RISC-V Target Machine ----
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H A DRISCVISelDAGToDAG.h1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V --
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H A DRISCVCallingConv.td1 //===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablege
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H A DRISCVFrameLowering.h1 //===-- RISCVFrameLowering.h - Define frame lowering for RISC-V -*- C++ -*-
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H A DRISCVInsertReadWriteCSR.cpp1 //===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR ----
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H A DRISCVRedundantCopyElimination.cpp1 //=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISC-V -----
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H A DRISCVInstrGISel.td1 //===-- RISCVInstrGISel.td - RISC-V GISel target pseudos ----*
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H A DRISCVTargetObjectFile.h1 //===-- RISCVTargetObjectFile.h - RISC-V Object Info ----
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/TargetInfo/
H A DRISCVTargetInfo.cpp1 //===-- RISCVTargetInfo.cpp - RISC-V Target Implementation ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
25 getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
27 getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
/freebsd-src/contrib/file/magic/Magdir/
H A Dacorn2 #----------
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H A Delf2 #----------
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/freebsd-src/contrib/llvm-project/clang/include/clang/Sema/
H A DRISCVIntrinsicManager.h1 //===- RISCVIntrinsicManager.h - RISC-V Intrinsic Handler -------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the RISCVIntrinsicManager, which handles RISC-V vector
12 //===----------------------------------------------------------------------===//
33 // Create RISC-V intrinsic and insert into symbol table and return true if
/freebsd-src/sys/crypto/des/
H A Ddes_ecb.c1 /* $KAME: des_ecb.c,v 1.6 2001/09/10 04:03:58 itojun Exp $ */
5 /* Copyright (C) 1995-1998 Eric Young (eay@mincom.oz.au)
12 * FREE FOR COMMERCIAL AND NON-COMMERCIAL USE
56 /* char *libdes_version="libdes v 3.24 - 20-Apr-1996 - eay"; */ /* wrong */
57 /* char *DES_version="DES part of SSLeay 0.6.4 30-Aug-1996"; */
66 const char *ptr,*unroll,*risc,*size; in des_options() local
75 risc="risc1"; in des_options()
78 risc="risc2"; in des_options()
81 risc="cisc"; in des_options()
92 sprintf(buf,"des(%s,%s,%s,%s)",ptr,risc,unroll,size); in des_options()
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DRISCVTargetDefEmitter.cpp1 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs -----
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/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsRISCVVector.def1 //==- BuiltinsRISCVVector.def - RISC-V Vector Builtin Database ---*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the RISC-V-specific builtin function database. Users of
12 //===----------------------------------------------------------------------===//
/freebsd-src/sys/riscv/riscv/
H A Dtimer.c1 /*-
2 * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
36 * RISC-V Timer
72 .tc_name = "RISC-
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