Lines Matching +full:risc +full:- +full:v

1 //===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for the RISC-V architecture.
11 //===----------------------------------------------------------------------===//
13 // The RISC-V calling convention is handled with custom code in
29 defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),
49 // Same as CSR_Interrupt, but including all 32-bit FP registers.
53 // Same as CSR_Interrupt, but including all 64-bit FP registers.
57 // Same as CSR_Interrupt, but excluding X16-X31.
61 // Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.
65 // Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.