Lines Matching +full:risc +full:- +full:v

1 //===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 // This file implements the machine function pass to insert read/write of CSR-s
9 // of the RISC-V instructions.
12 // -Writing and saving frm before an RVV floating-point instruction with a
15 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "riscv-insert-read-write-csr"
24 #define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
27     DisableFRMInsertOpt("riscv-disable-frm-insert-opt", cl::init(false),
89         BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRM))
117       MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
118       SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
119       BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm), SavedFRM)
123       BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRMImm))
133         BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
159     MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
160     Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
161     BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
168         BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))