Lines Matching +full:risc +full:- +full:v

1 //=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISC-V -----=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
22 // do on RISC-V since branches can't have immediates.
24 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "riscv-copyelim"
59     return "RISC-V Redundant Copy Elimination";
70 INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
71                 "RISC-V Redundant Copy Elimination", false, false)
97   if (PredMBB->succ_size() != 2)
102   if (TII->analyzeBranch(*PredMBB, TBB, FBB, Cond, /*AllowModify*/ false) ||
120     if (MI->isCopy() && MI->getOperand(0).isReg() &&
121         MI->getOperand(1).isReg()) {
122       Register DefReg = MI->getOperand(0).getReg();
123       Register SrcReg = MI->getOperand(1).getReg();
125       if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) &&
128         LLVM_DEBUG(MI->print(dbgs()));
130         MI->eraseFromParent();
138     if (MI->modifiesRegister(TargetReg, TRI))
145   MachineBasicBlock::iterator CondBr = PredMBB->getFirstTerminator();
146   assert((CondBr->getOpcode() == RISCV::BEQ ||
147           CondBr->getOpcode() == RISCV::BNE) &&
149   assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register");
151   // Otherwise, we have to fixup the use-def chain, starting with the
153   CondBr->clearRegisterKills(TargetReg, TRI);
155   // Add newly used reg to the block's live-in list if it isn't there already.