Lines Matching +full:risc +full:- +full:v

1 //===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
12 // RISC-V subtarget features and instruction predicates.
13 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // RISC-V profiles supported.
19 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
40 // RISC-V macro fusions.
41 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
46 // RISC-V Scheduling Models
47 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
58 // RISC-V processors supported.
59 //===----------------------------------------------------------------------===//
63 //===----------------------------------------------------------------------===//
64 // Define the RISC-V target.
65 //===----------------------------------------------------------------------===//