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/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dset-gpr-idx-peephole.mir10 …_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
11 …; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit…
12 …; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit…
14 …_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
15 …$vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr…
17 …_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
18 …$vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgp…
28 …; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, impli…
29 …; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit…
31 …; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit…
[all …]
H A Dmerge-m0.mir1 # RUN: llc -mtriple=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copi…
3 # GCN-LABEL: name: merge-m0-many-init
52 name: merge-m0-many-init
63 SI_INIT_M0 -1, implicit-def $m0
64 DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
65 SI_INIT_M0 -1, implicit-def $m0
66 DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
67 SI_INIT_M0 65536, implicit-def $m0
68 DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
69 SI_INIT_M0 65536, implicit-def $m0
[all …]
H A Ddebug-value-scheduler.mir27 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
33 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
34 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
35 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
36 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
37 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
38 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
39 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
40 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
41 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dfold-operands-remove-m0-redef.mir36 ; GCN-NEXT: $m0 = COPY [[COPY1]]
37 …; GCN-NEXT: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit …
38 …; GCN-NEXT: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implici…
41 $m0 = COPY %1
42 %2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load (s32))
43 $m0 = COPY %1
44 %3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load (s32))
62 ; GCN-NEXT: $m0 = COPY [[COPY1]]
63 …; GCN-NEXT: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit …
64 …; GCN-NEXT: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implici…
[all …]
H A Dspill-m0.ll11 ; GCN-NEXT: s_mov_b32 m0, 0
13 ; GCN-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
27 ; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]
32 ; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]
34 ; GCN: s_add_i32 s{{[0-9]+}}, m0, 1
37 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
46 %foo = call i32 asm sideeffect "s_add_i32 $0, $1, 1", "=s,{m0}"(i32 %m0) #
[all...]
H A Dmachine-scheduler-sink-trivial-remats.mir14 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
15 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
16 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
17 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
18 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
19 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
20 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
21 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
22 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
23 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all...]
H A Dmachine-scheduler-sink-trivial-remats-debug.mir22 …om: %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0
27 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
28 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
29 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
30 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
31 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
32 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
33 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
34 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
35 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dload-local-i1.ll7 ; SICIVI: s_mov_b32 m0
8 ; GFX9-NOT: m0
24 ; SICIVI: s_mov_b32 m0
25 ; GFX9-NOT: m0
33 ; SICIVI: s_mov_b32 m0
34 ; GFX9-NOT: m0
42 ; SICIVI: s_mov_b32 m0
43 ; GFX9-NOT: m0
51 ; SICIVI: s_mov_b32 m0
52 ; GFX9-NOT: m0
[all...]
H A Dgws-hazards.mir19 ; GFX9-NEXT: $m0 = S_MOV_B32 -1
21 ; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
26 ; VI-NEXT: $m0 = S_MOV_B32 -1
28 ; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
33 ; CI-NEXT: $m0 = S_MOV_B32 -1
34 ; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
39 ; SI-NEXT: $m0 = S_MOV_B32 -1
40 ; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
45 ; GFX10-NEXT: $m0 = S_MOV_B32 -1
46 ; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
[all …]
H A Dlocal-atomics64.ll6 ; SICIVI: s_mov_b32 m0
7 ; GFX9-NOT: m0
18 ; SICIVI: s_mov_b32 m0
19 ; GFX9-NOT: m0
31 ; SICIVI: s_mov_b32 m0
32 ; GFX9-NOT: m0
44 ; SICIVI: s_mov_b32 m0
45 ; GFX9-NOT: m0
57 ; SICIVI: s_mov_b32 m0
58 ; GFX9-NOT: m0
[all …]
H A Dlocal-atomics.ll10 ; SICIVI-DAG: s_mov_b32 m0
11 ; GFX9-NOT: m0
26 ; SICIVI: s_mov_b32 m0
27 ; GFX9-NOT: m0
40 ; SICIVI: s_mov_b32 m0
41 ; GFX9-NOT: m0
57 ; SICIVI-DAG: s_mov_b32 m0
58 ; GFX9-NOT: m0
73 ; SICIVI: s_mov_b32 m0
74 ; GFX9-NOT: m0
[all …]
H A Ddebug-value-scheduler-liveins.mir18 %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
24 %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
25 %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
26 %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
27 %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
28 %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
29 %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
30 %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
31 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
32 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
[all …]
H A Dllvm.amdgcn.interp.f16.ll6 define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
9 ; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
23 ; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
37 ; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
50 %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
51 %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
52 %p1_1 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 1, i32 %m0)
53 %p2_1 = call half @llvm.amdgcn.interp.p2.f16(float %p1_1, float %j, i32 1, i32 2, i1 1, i32 %m0)
58 ; check that m0 is setup correctly before the interp p1 instruction
59 define amdgpu_ps half @interp_p1_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
[all …]
H A Dhazard.mir7 # GCN: $m0 = S_MOV_B32
28 $m0 = S_MOV_B32 killed $sgpr7
30 $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
37 # GCN: $m0 = S_MOV_B32
57 $m0 = S_MOV_B32 killed $sgpr7
59 $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
64 # from adding s_nop instructions between m0 update and s_sendmsg.
70 # GCN: S_SENDMSG 3, implicit $exec, implicit $m0
75 $m0 = S_MOV_B32 killed $sgpr12
83 S_SENDMSG 3, implicit $exec, implicit $m0
[all …]
H A Dremat-dead-subreg.mir13 ; GCN: $m0 = IMPLICIT_DEF
14 ; GCN-NEXT: renamable $sgpr0_sgpr1 = S_MOV_B64 1, implicit $m0
17 ; GCN-NEXT: renamable $sgpr2 = S_MOV_B32 2, implicit $m0
18 ; GCN-NEXT: renamable $sgpr1 = S_MOV_B32 3, implicit $m0
23 $m0 = IMPLICIT_DEF
24 %0:sreg_64_xexec = S_MOV_B64 1, implicit $m0
26 %2:sreg_32 = S_MOV_B32 2, implicit $m0
27 %3:sreg_32 = S_MOV_B32 3, implicit $m0
38 ; GCN: $m0 = IMPLICIT_DEF
39 ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_MOV_B64 1, implicit $m0
[all …]
H A Dfold-reload-into-m0.mir4 # Test that a spill of a copy of m0 is not folded to be a spill of m0 directly.
16 ; CHECK: S_NOP 0, implicit-def $m0
17 ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $m0
23 ; CHECK-NEXT: $m0 = S_MOV_B32 killed $sgpr0
25 ; CHECK-NEXT: S_SENDMSG 0, implicit $m0, implicit $exec
26 S_NOP 0, implicit-def $m0
27 %0:sreg_32 = COPY $m0
29 $m0 = COPY %0
30 S_SENDMSG 0, implicit $m0, implici
[all...]
H A Dllvm.amdgcn.sendmsg.ll6 ; GCN: s_mov_b32 m0, 0
7 ; GCN-NOT: s_mov_b32 m0
16 ; GCN: s_mov_b32 m0, 0
17 ; GCN-NOT: s_mov_b32 m0
26 ; GCN: s_mov_b32 m0, 0
27 ; GCN-NOT: s_mov_b32 m0
36 ; GCN: s_mov_b32 m0, 0
37 ; GCN-NOT: s_mov_b32 m0
46 ; GCN: s_mov_b32 m0, 0
47 ; GCN-NOT: s_mov_b32 m0
[all …]
H A Datomic_load_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
56 ; GFX9-NOT: s_mov_b32 m0
57 ; CI-NEXT: s_mov_b32 m0
[all …]
H A Dlds-dma-waitcnt.mir12 $m0 = S_MOV_B32 0
13 …gpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from …
14 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `ptr addr…
29 $m0 = S_MOV_B32 0
30 …gpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from …
31 …gpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from …
32 …$vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `ptr addr…
46 $m0 = S_MOV_B32 0
47 …gpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from …
63 $m0 = S_MOV_B32 0
[all …]
H A Dstore-local.ll8 ; SICIVI: s_mov_b32 m0
9 ; GFX9-NOT: m0
23 ; SICIVI: s_mov_b32 m0
24 ; GFX9-NOT: m0
37 ; SICIVI: s_mov_b32 m0
38 ; GFX9-NOT: m0
51 ; SICIVI: s_mov_b32 m0
52 ; GFX9-NOT: m0
66 ; SICIVI: s_mov_b32 m0
67 ; GFX9-NOT: m0
[all …]
H A Dload-local-i8.ll12 ; SICIVI: s_mov_b32 m0
13 ; GFX9-NOT: m0
26 ; SICIVI: s_mov_b32 m0
27 ; GFX9-NOT: m0
39 ; GFX9-NOT: m0
51 ; GFX9-NOT: m0
63 ; GFX9-NOT: m0
76 ; GFX9-NOT: m0
92 ; GFX9-NOT: m0
94 ; SICIVI: s_mov_b32 m0
[all...]
H A Dload-local-i32.ll14 ; SICIVI: s_mov_b32 m0, -1
15 ; GFX9-NOT: m0
27 ; SICIVI: s_mov_b32 m0, -1
28 ; GFX9-NOT: m0
39 ; SICIVI: s_mov_b32 m0, -1
40 ; GFX9-NOT: m0
53 ; SICIVI: s_mov_b32 m0, -1
54 ; GFX9-NOT: m0
66 ; SICIVI: s_mov_b32 m0, -1
67 ; GFX9-NOT: m0
[all …]
H A Datomic_store_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
56 ; GFX9-NOT: s_mov_b32 m0
57 ; CI-NEXT: s_mov_b32 m0
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.writelane.ll11 ; GFX7-NEXT: s_mov_b32 m0, s3
12 ; GFX7-NEXT: v_writelane_b32 v0, s2, m0
18 ; GFX8-NEXT: s_mov_b32 m0, s3
19 ; GFX8-NEXT: v_writelane_b32 v0, s2, m0
36 ; GFX7-NEXT: s_mov_b32 m0, s3
37 ; GFX7-NEXT: v_writelane_b32 v0, s2, m0
43 ; GFX8-NEXT: s_mov_b32 m0, s3
44 ; GFX8-NEXT: v_writelane_b32 v0, s2, m0
62 ; GFX7-NEXT: s_mov_b32 m0, s2
63 ; GFX7-NEXT: v_writelane_b32 v0, s0, m0
[all …]
/llvm-project/llvm/test/MC/Hexagon/
H A Dv65_all.s16 if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
17 # CHECK: 2f00c400 { if (q0) vtmp.w = vgather(r0,m0,v0.w).w }
21 vscatter(R0,M0,V0.w).w=V0
22 # CHECK: 2f20c000 { vscatter(r0,m0,v0.w).w = v0 }
26 vscatter(R0,M0,V0.h).h=V0
27 # CHECK: 2f20c020 { vscatter(r0,m0,v0.h).h = v0 }
36 if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h
37 # CHECK: 2f00c600 { if (q0) vtmp.h = vgather(r0,m0,v1:0.w).h }
46 vtmp.h=vgather(R0,M0,V0.h).h
47 # CHECK: 2f00c100 { vtmp.h = vgather(r0,m0,v0.h).h }
[all …]

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