Lines Matching full:m0

6 define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
9 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
23 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
37 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, s2
50   %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
51   %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
52   %p1_1 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 1, i32 %m0)
53   %p2_1 = call half @llvm.amdgcn.interp.p2.f16(float %p1_1, float %j, i32 1, i32 2, i1 1, i32 %m0)
58 ; check that m0 is setup correctly before the interp p1 instruction
59 define amdgpu_ps half @interp_p1_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
63 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, 0
65 ; GFX9-32BANK-NEXT:    s_mov_b32 s3, m0
67 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
79 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, 0
81 ; GFX8-32BANK-NEXT:    s_mov_b32 s3, m0
83 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
95 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, 0
97 ; GFX8-16BANK-NEXT:    s_mov_b32 s3, m0
98 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, s2
109   %mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
110   %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
111   %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
118 ; check that m0 is setup correctly before the interp p2 instruction
119 define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
122 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
127 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, 0
129 ; GFX9-32BANK-NEXT:    s_mov_b32 s0, m0
131 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
139 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
144 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, 0
146 ; GFX8-32BANK-NEXT:    s_mov_b32 s0, m0
148 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
156 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, s2
162 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, 0
164 ; GFX8-16BANK-NEXT:    s_mov_b32 s0, m0
166 ; GFX8-16BANK-NEXT:    s_mov_b32 m0, s2
172   %p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
173   %mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
174   %p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
181 ; float @llvm.amdgcn.interp.p1.f16(i, attrchan, attr, high, m0)
183 ; half @llvm.amdgcn.interp.p1.f16(p1, j, attrchan, attr, high, m0)