xref: /llvm-project/llvm/test/CodeGen/AMDGPU/gws-hazards.mir (revision e7900e695e7dfb36be8651d914a31f42a5d6c634) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX9 %s
3# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=VI %s
4# RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=CI %s
5# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=SI %s
6# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
7# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
8
9---
10name: m0_gws_init0
11tracksRegLiveness: true
12body: |
13
14  bb.0:
15    liveins: $vgpr0
16    ; GFX9-LABEL: name: m0_gws_init0
17    ; GFX9: liveins: $vgpr0
18    ; GFX9-NEXT: {{  $}}
19    ; GFX9-NEXT: $m0 = S_MOV_B32 -1
20    ; GFX9-NEXT: S_NOP 0
21    ; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
22    ;
23    ; VI-LABEL: name: m0_gws_init0
24    ; VI: liveins: $vgpr0
25    ; VI-NEXT: {{  $}}
26    ; VI-NEXT: $m0 = S_MOV_B32 -1
27    ; VI-NEXT: S_NOP 0
28    ; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
29    ;
30    ; CI-LABEL: name: m0_gws_init0
31    ; CI: liveins: $vgpr0
32    ; CI-NEXT: {{  $}}
33    ; CI-NEXT: $m0 = S_MOV_B32 -1
34    ; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
35    ;
36    ; SI-LABEL: name: m0_gws_init0
37    ; SI: liveins: $vgpr0
38    ; SI-NEXT: {{  $}}
39    ; SI-NEXT: $m0 = S_MOV_B32 -1
40    ; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
41    ;
42    ; GFX10-LABEL: name: m0_gws_init0
43    ; GFX10: liveins: $vgpr0
44    ; GFX10-NEXT: {{  $}}
45    ; GFX10-NEXT: $m0 = S_MOV_B32 -1
46    ; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
47    $m0 = S_MOV_B32 -1
48    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
49
50...
51
52---
53name: m0_gws_init1
54tracksRegLiveness: true
55body: |
56
57  bb.0:
58    ; GFX9-LABEL: name: m0_gws_init1
59    ; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
60    ; GFX9-NEXT: $m0 = S_MOV_B32 -1
61    ; GFX9-NEXT: S_NOP 0
62    ; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
63    ;
64    ; VI-LABEL: name: m0_gws_init1
65    ; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
66    ; VI-NEXT: $m0 = S_MOV_B32 -1
67    ; VI-NEXT: S_NOP 0
68    ; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
69    ;
70    ; CI-LABEL: name: m0_gws_init1
71    ; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
72    ; CI-NEXT: $m0 = S_MOV_B32 -1
73    ; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
74    ;
75    ; SI-LABEL: name: m0_gws_init1
76    ; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
77    ; SI-NEXT: $m0 = S_MOV_B32 -1
78    ; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
79    ;
80    ; GFX10-LABEL: name: m0_gws_init1
81    ; GFX10: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
82    ; GFX10-NEXT: $m0 = S_MOV_B32 -1
83    ; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
84    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
85    $m0 = S_MOV_B32 -1
86    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
87
88...
89
90# Test a typical situation where m0 needs to be set from a VGPR
91# through readfirstlane
92---
93name: m0_gws_readlane
94tracksRegLiveness: true
95body: |
96
97  bb.0:
98    liveins: $vgpr0, $vgpr1
99
100    ; GFX9-LABEL: name: m0_gws_readlane
101    ; GFX9: liveins: $vgpr0, $vgpr1
102    ; GFX9-NEXT: {{  $}}
103    ; GFX9-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
104    ; GFX9-NEXT: $m0 = S_MOV_B32 $sgpr0
105    ; GFX9-NEXT: S_NOP 0
106    ; GFX9-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
107    ;
108    ; VI-LABEL: name: m0_gws_readlane
109    ; VI: liveins: $vgpr0, $vgpr1
110    ; VI-NEXT: {{  $}}
111    ; VI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
112    ; VI-NEXT: $m0 = S_MOV_B32 $sgpr0
113    ; VI-NEXT: S_NOP 0
114    ; VI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
115    ;
116    ; CI-LABEL: name: m0_gws_readlane
117    ; CI: liveins: $vgpr0, $vgpr1
118    ; CI-NEXT: {{  $}}
119    ; CI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
120    ; CI-NEXT: $m0 = S_MOV_B32 $sgpr0
121    ; CI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
122    ;
123    ; SI-LABEL: name: m0_gws_readlane
124    ; SI: liveins: $vgpr0, $vgpr1
125    ; SI-NEXT: {{  $}}
126    ; SI-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
127    ; SI-NEXT: $m0 = S_MOV_B32 $sgpr0
128    ; SI-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
129    ;
130    ; GFX10-LABEL: name: m0_gws_readlane
131    ; GFX10: liveins: $vgpr0, $vgpr1
132    ; GFX10-NEXT: {{  $}}
133    ; GFX10-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
134    ; GFX10-NEXT: $m0 = S_MOV_B32 $sgpr0
135    ; GFX10-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
136    $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
137    $m0 = S_MOV_B32 $sgpr0
138    DS_GWS_INIT  $vgpr0, 0, implicit $m0, implicit $exec
139
140...
141