/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIOptimizeVGPRLiveRange.cpp | 214 for (auto &UseMI : MRI->use_nodbg_instructions(Reg)) { findNonPHIUsesInBlock() local 305 auto *UseMI = I->getParent(); collectCandidateRegisters() local 430 auto *UseMI = I->getParent(); updateLiveRangeInThenRegion() local 521 auto *UseMI = O.getParent(); optimizeLiveRange() local 565 auto *UseMI = O.getParent(); optimizeWaterfallLiveRange() local [all...] |
H A D | SIFoldOperands.cpp | 25 MachineInstr *UseMI; global() member 180 frameIndexMayFold(const MachineInstr & UseMI,int OpNo,const MachineOperand & OpToFold) const frameIndexMayFold() argument 690 tryToFoldACImm(const MachineOperand & OpToFold,MachineInstr * UseMI,unsigned UseOpIdx,SmallVectorImpl<FoldCandidate> & FoldList) const tryToFoldACImm() argument 757 foldOperand(MachineOperand & OpToFold,MachineInstr * UseMI,int UseOpIdx,SmallVectorImpl<FoldCandidate> & FoldList,SmallVectorImpl<MachineInstr * > & CopiesToReplace) const foldOperand() argument 1380 for (auto &UseMI : foldInstOperand() local 1401 MachineInstr *UseMI = U->getParent(); foldInstOperand() local 1788 MachineInstr *UseMI = Op->getParent(); tryFoldRegSequence() local [all...] |
H A D | SIFixSGPRCopies.cpp | 234 const auto *UseMI = MO.getParent(); tryChangeVGPRtoSGPRinCopy() local 805 const MachineInstr *UseMI = Use.getParent(); processPHINode() local [all...] |
/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonOptAddrMode.cpp | 191 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode(); canRemoveAddasl() local 324 MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode(); isSafeToExtLR() local 474 MachineInstr *UseMI = OwnerN.Addr->getCode(); processAddUses() local 493 updateAddUses(MachineInstr * AddMI,MachineInstr * UseMI) updateAddUses() argument 701 MachineInstr *UseMI = UseIA.Addr->getCode(); changeAddAsl() local 747 xformUseMI(MachineInstr * TfrMI,MachineInstr * UseMI,NodeAddr<UseNode * > UseN,unsigned UseMOnum) xformUseMI() argument 828 MachineInstr *UseMI = OwnerN.Addr->getCode(); processBlock() local [all...] |
/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineTraceMetrics.cpp | 697 static bool getDataDeps(const MachineInstr &UseMI, in getPHIDeps() argument 669 getDataDeps(const MachineInstr & UseMI,SmallVectorImpl<DataDep> & Deps,const MachineRegisterInfo * MRI) getDataDeps() argument 716 updatePhysDepsDownwards(const MachineInstr * UseMI,SmallVectorImpl<DataDep> & Deps,SparseSet<LiveRegUnit> & RegUnits,const TargetRegisterInfo * TRI) updatePhysDepsDownwards() argument 795 updateDepth(MachineTraceMetrics::TraceBlockInfo & TBI,const MachineInstr & UseMI,SparseSet<LiveRegUnit> & RegUnits) updateDepth() argument 834 updateDepth(const MachineBasicBlock * MBB,const MachineInstr & UseMI,SparseSet<LiveRegUnit> & RegUnits) updateDepth() argument 962 pushDepHeight(const DataDep & Dep,const MachineInstr & UseMI,unsigned UseHeight,MIHeightMap & Heights,const TargetSchedModel & SchedModel,const TargetInstrInfo * TII) pushDepHeight() argument [all...] |
H A D | RegisterScavenging.cpp | 225 spill(Register Reg,const TargetRegisterClass & RC,int SPAdj,MachineBasicBlock::iterator Before,MachineBasicBlock::iterator & UseMI) spill() argument 304 MachineBasicBlock::iterator UseMI; scavengeRegisterBackwards() local
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H A D | TargetSchedule.cpp | 175 computeOperandLatency(const MachineInstr * DefMI,unsigned DefOperIdx,const MachineInstr * UseMI,unsigned UseOperIdx) const computeOperandLatency() argument
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H A D | TailDuplicator.cpp | 243 SSAUpdate.GetValueInMiddleOfBlock(UseMI->getParent(), true)); in tailDuplicateAndUpdate() local 229 MachineInstr *UseMI = UseMO.getParent(); tailDuplicateAndUpdate() local
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H A D | LiveRangeEdit.cpp | 209 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local [all...] |
H A D | PeepholeOptimizer.cpp | 547 MachineInstr *UseMI = UseMO.getParent(); INITIALIZE_PASS_DEPENDENCY() local 619 MachineInstr *UseMI = UseMO->getParent(); INITIALIZE_PASS_DEPENDENCY() local 1942 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) { getNextSourceFromBitcast() local [all...] |
H A D | MachineSSAUpdater.cpp | 230 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
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H A D | DetectDeadLanes.cpp | 339 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
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/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16RegisterInfo.cpp | 58 saveScavengerRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,MachineBasicBlock::iterator & UseMI,const TargetRegisterClass * RC,Register Reg) const saveScavengerRegister() argument
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/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVRegisterBankInfo.cpp | 227 __anon844b64a60102(const MachineInstr &UseMI) anyUseOnlyUseFP() argument 425 __anon844b64a60202(const MachineInstr &UseMI) getInstrMapping() argument
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/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Localizer.cpp | 128 MachineInstr &UseMI = *MOUse.getParent(); in localizeInterBlock() local
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/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 286 MachineInstr *UseMI = UseMO.getParent(); processBlock() local
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H A D | PPCInstrInfo.cpp | 170 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency() argument 2047 onlyFoldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,Register Reg) const onlyFoldImmediate() argument 2118 foldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,Register Reg,MachineRegisterInfo * MRI) const foldImmediate() argument 2443 MachineInstr *UseMI = &*I; optimizeCompareInstr() local 2506 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg); optimizeCompareInstr() local 2632 MachineInstr *UseMI = &*I; optimizeCompareInstr() local [all...] |
/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCRegisterBankInfo.cpp | 179 __anonf172b2db0102(const MachineInstr &UseMI) getInstrMapping() argument
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64Subtarget.cpp | 504 const MachineInstr *UseMI = Use->getInstr(); adjustSchedDependency() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64RegisterBankInfo.cpp | 532 __anon9da5ff2a0202(const MachineInstr &UseMI) isPHIWithFPContraints() argument 898 __anon9da5ff2a0402(const MachineInstr &UseMI) getInstrMapping() argument
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 381 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps() local [all...] |
/llvm-project/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
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/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVPreLegalizer.cpp | 472 MachineInstr &UseMI = *MRI.use_instr_begin(Reg); generateAssignInstrs() local 586 MachineInstr &UseMI = *MRI.use_instr_begin(DstReg); processInstrsWithTypeFolding() local
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/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86RegisterBankInfo.cpp | 379 __anon4fe9c1a40202(const MachineInstr &UseMI) getInstrMapping() argument
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastPreTileConfig.cpp | 218 reload(MachineBasicBlock::iterator UseMI,Register OrigReg,MachineOperand * RowMO,MachineOperand * ColMO) reload() argument [all...] |