Lines Matching defs:UseMI

695 // Get the input data dependencies that must be ready before UseMI can issue.
696 // Return true if UseMI has any physreg operands.
697 static bool getDataDeps(const MachineInstr &UseMI,
701   if (UseMI.isDebugInstr())
705   for (const MachineOperand &MO : UseMI.operands()) {
725 static void getPHIDeps(const MachineInstr &UseMI,
732   assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI");
733   for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) {
734     if (UseMI.getOperand(i + 1).getMBB() == Pred) {
735       Register Reg = UseMI.getOperand(i).getReg();
742 // Identify physreg dependencies for UseMI, and update the live regunit
744 static void updatePhysDepsDownwards(const MachineInstr *UseMI,
751   for (const MachineOperand &MO : UseMI->operands()) {
775   // Update RegUnits to reflect live registers after UseMI.
784          TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) {
786       LRU.MI = UseMI;
823 updateDepth(MachineTraceMetrics::TraceBlockInfo &TBI, const MachineInstr &UseMI,
827   if (UseMI.isPHI())
828     getPHIDeps(UseMI, Deps, TBI.Pred, MTM.MRI);
829   else if (getDataDeps(UseMI, Deps, MTM.MRI))
830     updatePhysDepsDownwards(&UseMI, Deps, RegUnits, MTM.TRI);
845         .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
849   InstrCycles &MICycles = Cycles[&UseMI];
855     LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
857     LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI);
862 updateDepth(const MachineBasicBlock *MBB, const MachineInstr &UseMI,
864   updateDepth(BlockInfo[MBB->getNumber()], UseMI, RegUnits);
924     for (const auto &UseMI : *MBB) {
925       updateDepth(TBI, UseMI, RegUnits);
958         // We may not know the UseMI of this dependency, if it came from the
959         // live-in list. SchedModel can handle a NULL UseMI.
988 // Push the height of DefMI upwards if required to match UseMI.
990 static bool pushDepHeight(const DataDep &Dep, const MachineInstr &UseMI,
996     UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
1311                                               const MachineInstr &UseMI) const {
1312   if (DefMI.getParent() == UseMI.getParent())
1316   const TraceBlockInfo &TBI = TE.BlockInfo[UseMI.getParent()->getNumber()];