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Searched defs:SrcRC (Results 1 – 25 of 33) sorted by relevance

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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp195 const TargetRegisterClass *SrcRC = SrcReg.isVirtual() getCopyRegClasses() local
209 isVGPRToSGPRCopy(const TargetRegisterClass * SrcRC,const TargetRegisterClass * DstRC,const SIRegisterInfo & TRI) isVGPRToSGPRCopy() argument
216 isSGPRToVGPRCopy(const TargetRegisterClass * SrcRC,const TargetRegisterClass * DstRC,const SIRegisterInfo & TRI) isSGPRToVGPRCopy() argument
285 const TargetRegisterClass *SrcRC, *DstRC; foldVGPRCopyIntoRegSequence() local
313 const TargetRegisterClass *SrcRC = foldVGPRCopyIntoRegSequence() local
631 const TargetRegisterClass *SrcRC, *DstRC; runOnMachineFunction() local
661 const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); runOnMachineFunction() local
764 const TargetRegisterClass *SrcRC, *DstRC; runOnMachineFunction() local
855 const TargetRegisterClass *SrcRC = tryMoveVGPRConstToSGPR() local
1064 const TargetRegisterClass *SrcRC = lowerVGPR2SGPRCopies() local
[all...]
H A DAMDGPUInstructionSelector.cpp114 const TargetRegisterClass *SrcRC constrainCopyLikeIntrin() local
147 const TargetRegisterClass *SrcRC selectCOPY() local
518 const TargetRegisterClass *SrcRC = selectG_EXTRACT() local
564 const TargetRegisterClass *SrcRC selectG_MERGE_VALUES() local
593 const TargetRegisterClass *SrcRC = selectG_UNMERGE_VALUES() local
2228 const TargetRegisterClass *SrcRC = selectG_TRUNC() local
2375 const TargetRegisterClass *SrcRC = selectG_SZA_EXT() local
2419 const TargetRegisterClass &SrcRC = InReg && DstSize > 32 ? selectG_SZA_EXT() local
2947 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); selectG_PTRMASK() local
3064 const TargetRegisterClass *SrcRC = selectG_EXTRACT_VECTOR_ELT() local
[all...]
H A DSIRegisterInfo.cpp2928 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
3008 const TargetRegisterClass *SrcRC = getRegClassForReg(MRI, MO.getReg()); getRegClassForOperandReg() local
3028 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
H A DSIFoldOperands.cpp841 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg); foldOperand() local
/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg() local
/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp284 const TargetRegisterClass *SrcRC = selectCopy() local
322 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); selectCopy() local
751 canTurnIntoCOPY(const TargetRegisterClass * DstRC,const TargetRegisterClass * SrcRC) canTurnIntoCOPY() argument
795 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); selectTruncOrPtrToInt() local
924 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); selectAnyext() local
1285 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); emitExtractSubreg() local
1323 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); emitInsertSubreg() local
[all...]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; processBlock() local
H A DPPCMIPeephole.cpp1238 const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); simplifyCode() local
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp246 auto SrcRC = MRI.getRegClass(SrcReg); runOnMachineFunction() local
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp133 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in foldSimpleCrossClassCopies() local
/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp314 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/CodeGen/
H A DMachineCombiner.cpp176 auto SrcRC = MRI->getRegClass(Src); isTransientMI() local
185 auto SrcRC = MRI->getRegClass(Src); isTransientMI() local
H A DTargetRegisterInfo.cpp382 shareSameRegisterFile(const TargetRegisterInfo & TRI,const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) shareSameRegisterFile() argument
412 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
H A DDetectDeadLanes.cpp73 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
H A DRegisterCoalescer.cpp492 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); setRegisters() local
1981 auto SrcRC = MRI->getRegClass(CP.getSrcReg()); joinCopy() local
H A DPeepholeOptimizer.cpp793 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); findNextSource() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp878 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
938 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp354 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp380 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp374 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
H A DInstrEmitter.cpp154 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp1053 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) const shouldCoalesce() argument
/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp66 getDstRC(const TargetRegisterClass * SrcRC,RegDomain Domain) getDstRC() argument
H A DX86RegisterInfo.cpp223 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h1114 shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS) shouldCoalesce() argument

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