Lines Matching defs:SrcRC

113                           const TargetRegisterClass *SrcRC) const;
292       const TargetRegisterClass *SrcRC =
296       if (SrcRC != DstRC) {
304             .addImm(getSubRegIndex(SrcRC));
330     const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
332     if (DstRC != SrcRC) {
765 // SrcRC lives on a 128-bit vector class.
767                             const TargetRegisterClass *SrcRC) {
770          (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass);
776     const TargetRegisterClass *SrcRC) const {
778   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
811   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
813   if (!DstRC || !SrcRC)
819   if (canTurnIntoCOPY(DstRC, SrcRC))
820     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
826   if (DstRC == SrcRC) {
839   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
841   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
940   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
945   if (canTurnIntoCOPY(SrcRC, DstRC))
946     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
951   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
958   if (SrcRC == DstRC) {
968       .addImm(getSubRegIndex(SrcRC));
1301   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1303   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
1305   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1339   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1342   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||