[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

[llvm] Remove redundant control flow statements (NFC) (#115831)

Identified with readability-redundant-control-flow.

Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole (#85451)

Fixes: https://github.com/llvm/llvm-project/issues/71030

Bug only happens in 64bit involving spills. Since

Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole (#85451)

Fixes: https://github.com/llvm/llvm-project/issues/71030

Bug only happens in 64bit involving spills. Since we don't know when the
spill will happen, all instructions in the chain used to deduce sign
extension for eliminating 'extsw' will need to be promoted to 64-bit
pseudo instructions.

The following instruction will promoted in PPCMIPeepholes: EXTSH, LHA,
ISEL to EXTSH8, LHA8, ISEL8

show more ...

[PowerPC] Ensure MI peephole knows about instr modified by combineRLWINM() (#97134)

Ensure registers used in instructions modified by `combineRLWINM()` are
added to list of `RegsToUpdate`.

[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)

- Add `MachineBlockFrequencyAnalysis`.
- Add `MachineBlockFrequencyPrinterPass`.
- Use `MachineBlockFrequencyInfoWrapperPass

[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)

- Add `MachineBlockFrequencyAnalysis`.
- Add `MachineBlockFrequencyPrinterPass`.
- Use `MachineBlockFrequencyInfoWrapperPass` in legacy pass manager.
- `LazyMachineBlockFrequencyInfo::print` is empty, drop it due to new
pass manager migration.

show more ...

[CodeGen][NewPM] Port `LiveVariables` to new pass manager (#97880)

- Port `LiveVariables` to new pass manager.
- Convert to `LiveVariablesWrapperPass` in legacy pass manager.

[PowerPC] Make verifier happy after peephole on MMA COPYs (#94321)

[CodeGen][NewPM] Split `MachinePostDominators` into a concrete analysis result (#95113)

`MachinePostDominators` version of #94571.

[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)

Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree v

[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)

Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree version of `DomTreeUpdater` to
handle `SplitCriticalEdge` in some CodeGen passes.

show more ...

[PPC]add DEBUG_COUNTER for PPCMIPeephole pass

[PowerPC] Fix missing kill flag update for XVCVDPSP transformations (#67997)

Add transformed register to kill flag work list for XVCVDPSP tranformations.

Ref: reviews.llvm.org/D133103

Use BlockFrequency type in more places (NFC) (#68266)

The `BlockFrequency` class abstracts `uint64_t` frequency values. Use it
more consistently in various APIs and disable implicit conversion to

Use BlockFrequency type in more places (NFC) (#68266)

The `BlockFrequency` class abstracts `uint64_t` frequency values. Use it
more consistently in various APIs and disable implicit conversion to
make usage more consistent and explicit.

- Use `BlockFrequency Freq` parameter for `setBlockFreq`,
`getProfileCountFromFreq` and `setBlockFreqAndScale` functions.
- Return `BlockFrequency` in `getEntryFreq()` functions.
- While on it change some `const BlockFrequency& Freq` parameters to
plain `BlockFreqency Freq`.
- Mark `BlockFrequency(uint64_t)` constructor as explicit.
- Add missing `BlockFrequency::operator!=`.
- Remove `uint64_t BlockFreqency::getMaxFrequency()`.
- Add `BlockFrequency BlockFrequency::max()` function.

show more ...

[PowerPC] A fix for D159073. Do not optimize when register classes are different in src and dst.

For example:
```
%298:g8rc = RLDICL %297:g8rc, 0, 48
%299:gprc = COPY killed %298.sub_32:g8rc
d

[PowerPC] A fix for D159073. Do not optimize when register classes are different in src and dst.

For example:
```
%298:g8rc = RLDICL %297:g8rc, 0, 48
%299:gprc = COPY killed %298.sub_32:g8rc
dead %498:gprc = ANDI_rec killed %299:gprc, 1, implicit-def dead $cr0, implicit-def $cr0gt
```

show more ...

Reland https://reviews.llvm.org/D159073.

The patch failed in test-suite due to a liveness error after rebasing on https://reviews.llvm.org/D133103, and now it's fixed.

```
[PowerPC][Peephole] Combi

Reland https://reviews.llvm.org/D159073.

The patch failed in test-suite due to a liveness error after rebasing on https://reviews.llvm.org/D133103, and now it's fixed.

```
[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

Summary: rldicl/rldicr can be eliminated if it's used to clear thehigh-order or low-order n bits and all bits cleared will be ANDed with 0 byandi/andis. Or they can be folded to `andi 0` if all bits to AND are alreadyzero in the input.

Reviewed By: qiucf, shchenz

Differential Revision: https://reviews.llvm.org/D159073
```

show more ...

Revert "[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel."

This reverts commit 2de74e1bd4d540063d7495fa6254781abd41e179.

A test-suite failure occurs due to this commit, will fix

Revert "[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel."

This reverts commit 2de74e1bd4d540063d7495fa6254781abd41e179.

A test-suite failure occurs due to this commit, will fix soon.

show more ...

[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

Summary: rldicl/rldicr can be eliminated if it's used to clear the high-order or low-order n bits and all bits cleared will be AN

[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

Summary: rldicl/rldicr can be eliminated if it's used to clear the high-order or low-order n bits and all bits cleared will be ANDed with 0 by andi/andis. Or they can be folded to `andi 0` if all bits to AND are already zero in the input.

Reviewed By: qiucf, shchenz

Differential Revision: https://reviews.llvm.org/D159073

show more ...

[PowerPC] Improve kill flag computation and add verification after MI peephole

The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations

[PowerPC] Improve kill flag computation and add verification after MI peephole

The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations require re-computation of kill flags but don't do a good job of re-computing them. This causes us to have very common failures when the compiler is built with expensive checks. Over time, we added and augmented a function that is supposed to go and fix up kill flags after each transformation but we keep missing cases.
This patch does the following:
- Removes the function to re-compute kill flags
- Adds LiveVariables to compute and maintain kill flags while transforming code
- Adds re-computation of kill flags for the post-RA peepholes for each block that contains a transformed instruction

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D133103

show more ...

[PowerPC] remove XXSWAPD after vector splat immediate

Redundant XXSWAPD has been observed on little-endian in D138883 test
case. Remove those associated with vector splat instructions.

Reviewed By:

[PowerPC] remove XXSWAPD after vector splat immediate

Redundant XXSWAPD has been observed on little-endian in D138883 test
case. Remove those associated with vector splat instructions.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D139193

show more ...

[PowerPC] Look through OR, AND, XOR instructions when checking a clear.

This patch adds the additional step of looking through AND, OR, XOR
instructions when we check the number of leading zeros.

R

[PowerPC] Look through OR, AND, XOR instructions when checking a clear.

This patch adds the additional step of looking through AND, OR, XOR
instructions when we check the number of leading zeros.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D149223

show more ...

[PPCMIPeephole] Fix incorrect compare elimination

D38236 moves a redundant compare instruction from the loop body to the
preheader.

It has a bug: when `MBB1 == &MBB2`, there may be only one compare

[PPCMIPeephole] Fix incorrect compare elimination

D38236 moves a redundant compare instruction from the loop body to the
preheader.

It has a bug: when `MBB1 == &MBB2`, there may be only one compare instruction in the
loop. The code will lift the compare instruction to the preheader, failing to
account for the change of the compare result in a tail call, leading to a miscompile.

Suppress the compare elimination to fix https://github.com/llvm/llvm-project/issues/62294

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D149030

show more ...

[PowerPC] remove XXSWAPD after load from CP which is a splat value

If the value from constant-pool is a splat value of vector type, do not
need swap after load from constant-pool.

Reviewed By: shch

[PowerPC] remove XXSWAPD after load from CP which is a splat value

If the value from constant-pool is a splat value of vector type, do not
need swap after load from constant-pool.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D139491

show more ...

[PowerPC] add a peephole to remove redundant swap instructions after vector splats on P8

Vector store on P8 little endian will have swap instruction added before
the store in PPCISelLowring. If the

[PowerPC] add a peephole to remove redundant swap instructions after vector splats on P8

Vector store on P8 little endian will have swap instruction added before
the store in PPCISelLowring. If the vector is generated by splat, the
swap instruction can be eliminated.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D139691

show more ...

[PowerPC] Do not convert lwz to lwa if the offset is not a multiple of 4

The transform that converts this checks the alignment of the global
object being accessed. However, there was no check for th

[PowerPC] Do not convert lwz to lwa if the offset is not a multiple of 4

The transform that converts this checks the alignment of the global
object being accessed. However, there was no check for the offset
within the global object which caused the compiler to produce a
DS relocation for an unaligned address.

show more ...

[Target] Use llvm::count{l,r}_{zero,one} (NFC)

[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC

Use isPhysical/isVirtual methods.