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Searched defs:Src1 (Results 1 – 25 of 56) sorted by relevance

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/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst()
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst()
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst()
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst()
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst()
192 static GenericValue executeICMP_EQ(GenericValue Src1, GenericValue Src2, in executeICMP_EQ()
206 static GenericValue executeICMP_NE(GenericValue Src1, GenericValue Src2, in executeICMP_NE()
220 static GenericValue executeICMP_ULT(GenericValue Src1, GenericValue Src2, in executeICMP_ULT()
234 static GenericValue executeICMP_SLT(GenericValue Src1, GenericValue Src2, in executeICMP_SLT()
248 static GenericValue executeICMP_UGT(GenericValue Src1, GenericValue Src2, in executeICMP_UGT()
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp143 const MachineOperand &Src1 = MI.getOperand(1); isLogicalOpOnExec() local
159 const MachineOperand &Src1 = MI.getOperand(1); isLogicalOpOnExec() local
537 MachineOperand &Src1 = SaveExecInst->getOperand(2); optimizeExecSequence() local
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); optimizeVCMPSaveExecSequence() local
686 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); tryRecordVCmpxAndSaveexecSequence() local
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H A DR600ExpandSpecialInstrs.cpp149 Register Src1 = in runOnMachineFunction() local
200 unsigned Src1 = 0; in runOnMachineFunction() local
H A DSIPeepholeSDWA.cpp590 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); matchSDWAOperand() local
628 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); matchSDWAOperand() local
663 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); matchSDWAOperand() local
710 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); matchSDWAOperand() local
1013 if (MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1)) { isConvertibleToSDWA() local
1071 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); convertToSDWA() local
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H A DAMDGPUCombinerHelper.cpp420 matchExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) matchExpandPromotedF16FMed3() argument
433 applyExpandPromotedF16FMed3(MachineInstr & MI,Register Src0,Register Src1,Register Src2) applyExpandPromotedF16FMed3() argument
H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
602 Value *Src1 = II.getArgOperand(1); instCombineIntrinsic() local
632 Value *Src1 = II.getArgOperand(1); instCombineIntrinsic() local
661 Value *Src1 = II.getArgOperand(1); instCombineIntrinsic() local
764 Value *Src1 = II.getArgOperand(1); instCombineIntrinsic() local
853 Value *Src1 = II.getArgOperand(1); instCombineIntrinsic() local
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H A DSIShrinkInstructions.cpp247 MachineOperand &Src1 = MI.getOperand(1); shrinkScalarCompare() local
419 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); shrinkMadFma() local
513 MachineOperand *Src1 = &MI.getOperand(2); shrinkScalarLogicOp() local
848 MachineOperand *Src1 = &MI.getOperand(2); runOnMachineFunction() local
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H A DGCNDPPCombine.cpp314 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); createDPPInst() local
490 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); createDPPInst() local
685 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); combineDPPMov() local
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H A DSIFoldOperands.cpp1231 MachineOperand *Src1 = getImmOrMaterializedImm(MI->getOperand(Src1Idx)); tryConstantFoldOp() local
1317 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); tryFoldCndMask() local
1358 Register Src1 = MI.getOperand(2).getReg(); tryFoldZeroHighBits() local
1530 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); isClamp() local
1667 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); isOMod() local
1704 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); isOMod() local
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H A DSIInstrInfo.cpp2722 swapSourceModifiers(MachineInstr & MI,MachineOperand & Src0,unsigned Src0OpName,MachineOperand & Src1,unsigned Src1OpName) const swapSourceModifiers() argument
2789 MachineOperand &Src1 = MI.getOperand(Src1Idx); commuteInstructionImpl() local
3524 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); foldImmediate() local
3933 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); convertToThreeAddress() local
4424 const MachineOperand *Src1 canShrink() local
4449 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1); canShrink() local
5005 const MachineOperand &Src1 = MI.getOperand(Src1Idx); verifyInstruction() local
5027 const MachineOperand &Src1 = MI.getOperand(Src1Idx); verifyInstruction() local
5852 MachineOperand &Src1 = MI.getOperand(Src1Idx); legalizeOperandsVOP2() local
5974 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]); legalizeOperandsVOP3() local
7220 MachineOperand &Src1 = Inst.getOperand(3); moveToVALUImpl() local
7545 MachineOperand &Src1 = Inst.getOperand(2); lowerSelect() local
7654 MachineOperand &Src1 = Inst.getOperand(2); lowerScalarXnor() local
7720 MachineOperand &Src1 = Inst.getOperand(2); splitScalarNotBinop() local
7749 MachineOperand &Src1 = Inst.getOperand(2); splitScalarBinOpN2() local
7841 MachineOperand &Src1 = Inst.getOperand(2); splitScalarSMulU64() local
7950 MachineOperand &Src1 = Inst.getOperand(2); splitScalarSMulPseudo() local
8009 MachineOperand &Src1 = Inst.getOperand(2); splitScalar64BitBinaryOp() local
8076 MachineOperand &Src1 = Inst.getOperand(2); splitScalar64BitXnor() local
8306 MachineOperand &Src1 = Inst.getOperand(2); movePackToVALU() local
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H A DAMDGPURegBankCombiner.cpp317 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); matchFPMed3ToClamp() local
H A DAMDGPUPostLegalizerCombiner.cpp420 Register Src1 = MI.getOperand(2).getReg(); in matchCombine_s_mul_u64() local
H A DSIISelLowering.cpp4963 MachineOperand &Src1 = MI.getOperand(3); EmitInstrWithCustomInserter() local
4986 MachineOperand &Src1 = MI.getOperand(2); EmitInstrWithCustomInserter() local
5038 MachineOperand &Src1 = MI.getOperand(2); EmitInstrWithCustomInserter() local
5120 MachineOperand &Src1 = MI.getOperand(3); EmitInstrWithCustomInserter() local
5277 const MachineOperand &Src1 = MI.getOperand(2); EmitInstrWithCustomInserter() local
6056 SDValue Src1 = N->getOperand(2); lowerFCMPIntrinsic() local
6124 __anon7a836d960102(SDValue Src0, SDValue Src1, SDValue Src2, MVT ValT) lowerLaneOp() argument
6161 SDValue Src1, Src2; lowerLaneOp() local
6313 SDValue Src1 = N->getOperand(2); ReplaceNodeResults() local
6325 SDValue Src1 = N->getOperand(2); ReplaceNodeResults() local
9496 SDValue Src1 = Op.getOperand(5); LowerINTRINSIC_VOID() local
10572 SDValue Src1 = Op.getOperand(1); LowerFDIV16() local
13272 SDValue Src1 = N->getOperand(1); performFMed3Combine() local
13309 SDValue Src1 = N->getOperand(1); performCvtPkRTZCombine() local
13813 placeSources(ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,SmallVectorImpl<DotSrc> & Src0s,SmallVectorImpl<DotSrc> & Src1s,int Step) placeSources() argument
13975 checkDot4MulSignedness(const SDValue & N,ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,const SDValue & S0Op,const SDValue & S1Op,const SelectionDAG & DAG) checkDot4MulSignedness() argument
14072 auto Src1 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(1)); performAddCombine() local
14096 auto Src1 = performAddCombine() local
14135 SDValue Src0, Src1; performAddCombine() local
15061 SDValue Src1 = Node->getOperand(3); PostISelFolding() local
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H A DSILoadStoreOptimizer.cpp1242 const auto *Src1 = TII->getNamedOperand(*Paired.I, OpName); copyFromSrcRegs() local
2020 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); processBaseWithConstOffset() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp151 MachineOperand &Src1 = MI.getOperand(1); runOnMachineFunction() local
168 MachineOperand &Src1 = MI.getOperand(1); runOnMachineFunction() local
H A DHexagonGenMux.cpp299 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock() local
205 getMuxOpcode(const MachineOperand & Src1,const MachineOperand & Src2) const getMuxOpcode() argument
H A DHexagonConstPropagation.cpp2575 const MachineOperand &Src1 = MI.getOperand(1); evaluateHexCompare() local
2598 evaluateHexCompare2(unsigned Opc,const MachineOperand & Src1,const MachineOperand & Src2,const CellMap & Inputs,bool & Result) evaluateHexCompare2() argument
2632 const MachineOperand &Src1 = MI.getOperand(1); evaluateHexLogical() local
3025 const MachineOperand &Src1 = MI.getOperand(1); rewriteHexConstUses() local
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/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp112 computeKnownBitsMin(Register Src0,Register Src1,KnownBits & Known,const APInt & DemandedElts,unsigned Depth) computeKnownBitsMin() argument
619 computeNumSignBitsMin(Register Src0,Register Src1,const APInt & DemandedElts,unsigned Depth) computeNumSignBitsMin() argument
747 Register Src1 = MI.getOperand(1).getReg(); computeNumSignBits() local
H A DCSEMIRBuilder.cpp262 const SrcOp &Src1 = SrcOps[1]; buildInstr() local
/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1763 buildAnd(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildAnd() argument
1785 buildXor(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildXor() argument
1951 buildFCopysign(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildFCopysign() argument
1985 buildSMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMin() argument
1991 buildSMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMax() argument
1997 buildUMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMin() argument
2003 buildUMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMax() argument
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/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp173 EmitTargetCodeForMemcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,SDValue Size,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForMemcmp() argument
225 EmitTargetCodeForStrcmp(SelectionDAG & DAG,const SDLoc & DL,SDValue Chain,SDValue Src1,SDValue Src2,MachinePointerInfo Op1PtrInfo,MachinePointerInfo Op2PtrInfo) const EmitTargetCodeForStrcmp() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp54 PairedCopy(const PPCInstrInfo * TII,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,Register Dest0,Register Dest1,Register Src0,Register Src1) PairedCopy() argument
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp122 Register Src0, Src1, Src2; in TEST_F() local
544 Register Src0, Src1; TEST_F() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp69 Register Src1 = MI.getOperand(1).getReg(); in matchExtractVecEltPairwiseAdd() local

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