Lines Matching defs:Src1
5082 MachineOperand &Src1 = MI.getOperand(3);
5090 .add(Src1);
5109 MachineOperand &Src1 = MI.getOperand(2);
5116 .add(Src1);
5131 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
5133 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
5163 MachineOperand &Src1 = MI.getOperand(2);
5170 .add(Src1);
5187 const TargetRegisterClass *Src1RC = Src1.isReg()
5188 ? MRI.getRegClass(Src1.getReg())
5199 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
5204 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
5246 MachineOperand &Src1 = MI.getOperand(3);
5257 if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) {
5260 .addReg(Src1.getReg());
5261 Src1.setReg(RegOp1);
5305 .add(Src1);
5407 const MachineOperand &Src1 = MI.getOperand(2);
5419 const TargetRegisterClass *Src1RC = Src1.isReg()
5420 ? MRI.getRegClass(Src1.getReg())
5431 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
5436 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
6186 SDValue Src1 = N->getOperand(2);
6192 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
6199 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, Src1,
6261 auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1,
6279 Operands.push_back(Src1);
6303 SDValue Src1, Src2;
6307 Src1 = N->getOperand(2);
6324 Src1 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src1) : Src1,
6333 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, MVT::i32);
6387 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6405 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1,
6415 : createLaneOp(Src0SubVec, Src1, Src2SubVec, SubVecVT));
6431 Src1 = DAG.getBitcast(VecVT, Src1);
6436 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VecVT);
6463 SDValue Src1 = N->getOperand(2);
6466 DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32, Src0, Src1);
6475 SDValue Src1 = N->getOperand(2);
6490 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
6492 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
9747 SDValue Src1 = Op.getOperand(5);
9757 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1), // src1
12531 // Since the mask is applied to Src1:Src2, Src1 bytes must be offset
13588 SDValue Src1 = N->getOperand(1);
13591 if (isClampZeroToOne(Src0, Src1)) {
13606 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13607 std::swap(Src0, Src1);
13609 if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2))
13610 std::swap(Src1, Src2);
13612 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13613 std::swap(Src0, Src1);
13615 if (isClampZeroToOne(Src1, Src2))
13625 SDValue Src1 = N->getOperand(1);
13626 if (Src0.isUndef() && Src1.isUndef())
14201 ByteProvider<SDValue> &Src1,
14205 assert(Src0.Src.has_value() && Src1.Src.has_value());
14210 Src1s.push_back({*Src1.Src, ((Src1.SrcOffset % 4) << 24) + 0x0c0c0c,
14211 Src1.SrcOffset / 4});
14216 std::pair<ByteProvider<SDValue>, ByteProvider<SDValue>> BPP = {Src0, Src1};
14218 BPP = {Src1, Src0};
14261 // for either Src0 or Src1, so just place them arbitrarily.
14271 {*Src1.Src,
14272 ((Src1.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
14273 Src1.SrcOffset / 4});
14361 ByteProvider<SDValue> &Src1, const SDValue &S0Op,
14463 auto Src1 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(1));
14464 if (!Src1)
14468 TempNode->getOperand(MulIdx), *Src0, *Src1,
14477 placeSources(*Src0, *Src1, Src0s, Src1s, I);
14487 auto Src1 =
14489 if (!Src1)
14492 TempNode->getOperand(AddIdx), *Src0, *Src1,
14500 placeSources(*Src0, *Src1, Src0s, Src1s, I + 1);
14526 SDValue Src0, Src1;
14563 Src1 = DAG.getBitcastedAnyExtOrTrunc(SecondEltOp, SL,
14570 Src1 = resolveSources(DAG, SL, Src1s, false, true);
14583 Src1, Src2, DAG.getTargetConstant(0, SL, MVT::i1));
15561 SDValue Src1 = Node->getOperand(3);
15566 (Src0 == Src1 || Src0 == Src2))
15583 if (Src1.isMachineOpcode() &&
15584 Src1.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
15585 Src0 = Src1;
15590 assert(Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF);
15592 Src1 = UndefReg;
15599 Ops[3] = Src1;
16356 auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs();
16364 KB.computeKnownBitsImpl(Src1, Known1, DemandedElts, Depth + 1);