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Searched defs:Src0 (Results 1 – 25 of 41) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1680 buildAnd(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildAnd() argument
1702 buildXor(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildXor() argument
1710 buildNot(const DstOp & Dst,const SrcOp & Src0) buildNot() argument
1718 buildNeg(const DstOp & Dst,const SrcOp & Src0) buildNeg() argument
1724 buildCTPOP(const DstOp & Dst,const SrcOp & Src0) buildCTPOP() argument
1729 buildCTLZ(const DstOp & Dst,const SrcOp & Src0) buildCTLZ() argument
1734 buildCTLZ_ZERO_UNDEF(const DstOp & Dst,const SrcOp & Src0) buildCTLZ_ZERO_UNDEF() argument
1739 buildCTTZ(const DstOp & Dst,const SrcOp & Src0) buildCTTZ() argument
1744 buildCTTZ_ZERO_UNDEF(const DstOp & Dst,const SrcOp & Src0) buildCTTZ_ZERO_UNDEF() argument
1749 buildBSwap(const DstOp & Dst,const SrcOp & Src0) buildBSwap() argument
1868 buildFCopysign(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildFCopysign() argument
1874 buildUITOFP(const DstOp & Dst,const SrcOp & Src0) buildUITOFP() argument
1879 buildSITOFP(const DstOp & Dst,const SrcOp & Src0) buildSITOFP() argument
1884 buildFPTOUI(const DstOp & Dst,const SrcOp & Src0) buildFPTOUI() argument
1889 buildFPTOSI(const DstOp & Dst,const SrcOp & Src0) buildFPTOSI() argument
1902 buildSMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMin() argument
1908 buildSMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildSMax() argument
1914 buildUMin(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMin() argument
1920 buildUMax(const DstOp & Dst,const SrcOp & Src0,const SrcOp & Src1) buildUMax() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp97 if (Src0.isReg()) { in foldImmediates() local
223 const MachineOperand &Src0 = MI.getOperand(0); shrinkScalarCompare() local
398 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); shrinkMadFma() local
492 MachineOperand *Src0 = &MI.getOperand(1); shrinkScalarLogicOp() local
825 MachineOperand *Src0 = &MI.getOperand(1); runOnMachineFunction() local
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H A DR600ExpandSpecialInstrs.cpp146 Register Src0 = in runOnMachineFunction() local
198 Register Src0 = in runOnMachineFunction() local
H A DSIPeepholeSDWA.cpp539 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
580 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
649 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
666 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); matchSDWAOperand() local
963 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { isConvertibleToSDWA() local
1015 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); convertToSDWA() local
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H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
605 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
635 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
664 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
767 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
854 Value *Src0 = II.getArgOperand(0); instCombineIntrinsic() local
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H A DAMDGPUCombinerHelper.cpp419 Register Src0, in matchExpandPromotedF16FMed3() argument
432 Register Src0, in applyExpandPromotedF16FMed3() argument
H A DSIOptimizeExecMasking.cpp536 MachineOperand &Src0 = SaveExecInst->getOperand(1); in optimizeExecSequence() local
583 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence() local
681 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence() local
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H A DSIModeRegister.cpp182 MachineOperand Src0 = MI.getOperand(1); in getInstructionMode() local
199 MachineOperand Src0 = MI.getOperand(1); in getInstructionMode() local
H A DSIFoldOperands.cpp1200 MachineOperand *Src0 = getImmOrMaterializedImm(MI->getOperand(Src0Idx)); tryConstantFoldOp() local
1298 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); tryFoldCndMask() local
1336 MachineOperand *Src0 = getImmOrMaterializedImm(MI.getOperand(1)); tryFoldZeroHighBits() local
1508 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isClamp() local
1640 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isOMod() local
1677 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); isOMod() local
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H A DGCNDPPCombine.cpp289 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); createDPPInst() local
680 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); combineDPPMov() local
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H A DGCNVOPDUtils.cpp83 const MachineOperand &Src0 = MI.getOperand(VOPD::Component::SRC0); in checkVOPDRegConstraints() local
H A DSIInstrInfo.cpp2668 swapSourceModifiers(MachineInstr & MI,MachineOperand & Src0,unsigned Src0OpName,MachineOperand & Src1,unsigned Src1OpName) const swapSourceModifiers() argument
2736 MachineOperand &Src0 = MI.getOperand(Src0Idx); commuteInstructionImpl() local
3460 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); FoldImmediate() local
3844 const MachineOperand *Src0 = &MI.getOperand(Src0Idx); convertToThreeAddress() local
3857 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); convertToThreeAddress() local
4878 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
4900 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
4969 const MachineOperand &Src0 = MI.getOperand(Src0Idx); verifyInstruction() local
5738 MachineOperand &Src0 = MI.getOperand(Src0Idx); legalizeOperandsVOP2() local
6550 Register Src0 = MI.getOperand(1).getReg(); legalizeOperands() local
6636 MachineOperand &Src0 = MI.getOperand(Src0Idx); legalizeOperands() local
7103 MachineOperand &Src0 = Inst.getOperand(2); moveToVALUImpl() local
7428 MachineOperand &Src0 = Inst.getOperand(1); lowerSelect() local
7537 MachineOperand &Src0 = Inst.getOperand(1); lowerScalarXnor() local
7603 MachineOperand &Src0 = Inst.getOperand(1); splitScalarNotBinop() local
7632 MachineOperand &Src0 = Inst.getOperand(1); splitScalarBinOpN2() local
7659 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitUnaryOp() local
7724 MachineOperand &Src0 = Inst.getOperand(1); splitScalarSMulU64() local
7833 MachineOperand &Src0 = Inst.getOperand(1); splitScalarSMulPseudo() local
7892 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitBinaryOp() local
7959 MachineOperand &Src0 = Inst.getOperand(1); splitScalar64BitXnor() local
8189 MachineOperand &Src0 = Inst.getOperand(1); movePackToVALU() local
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H A DAMDGPUPostLegalizerCombiner.cpp344 Register Src0; matchCvtF32UByteN() local
440 Register Src0 = MI.getOperand(1).getReg(); matchCombine_s_mul_u64() local
H A DSILoadStoreOptimizer.cpp1580 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); mergeTBufferStorePair() local
1678 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); mergeFlatStorePair() local
1909 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); mergeBufferStorePair() local
2077 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); processBaseWithConstOffset() local
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H A DAMDGPURegBankCombiner.cpp316 MachineInstr *Src0 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in matchFPMed3ToClamp() local
H A DSIISelLowering.cpp4731 MachineOperand &Src0 = MI.getOperand(2); EmitInstrWithCustomInserter() local
4754 MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
4806 MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
4888 MachineOperand &Src0 = MI.getOperand(2); EmitInstrWithCustomInserter() local
5047 const MachineOperand &Src0 = MI.getOperand(1); EmitInstrWithCustomInserter() local
5821 SDValue Src0 = N->getOperand(1); lowerFCMPIntrinsic() local
5900 SDValue Src0 = N->getOperand(1); ReplaceNodeResults() local
5912 SDValue Src0 = N->getOperand(1); ReplaceNodeResults() local
8179 SDValue Src0 = Param->isAllOnes() ? Numerator : Denominator; LowerINTRINSIC_WO_CHAIN() local
9263 SDValue Src0 = Op.getOperand(4); LowerINTRINSIC_VOID() local
10384 SDValue Src0 = Op.getOperand(0); LowerFDIV16() local
12977 SDValue Src0 = N->getOperand(0); performFMed3Combine() local
13014 SDValue Src0 = N->getOperand(0); performCvtPkRTZCombine() local
13512 placeSources(ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,SmallVectorImpl<std::pair<SDValue,unsigned>> & Src0s,SmallVectorImpl<std::pair<SDValue,unsigned>> & Src1s,int Step) placeSources() argument
13671 checkDot4MulSignedness(const SDValue & N,ByteProvider<SDValue> & Src0,ByteProvider<SDValue> & Src1,const SDValue & S0Op,const SDValue & S1Op,const SelectionDAG & DAG) checkDot4MulSignedness() argument
13766 auto Src0 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0)); performAddCombine() local
13789 auto Src0 = performAddCombine() local
13832 SDValue Src0, Src1; performAddCombine() local
14749 SDValue Src0 = Node->getOperand(1); PostISelFolding() local
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H A DSIFixSGPRCopies.cpp710 MachineOperand &Src0 = MI.getOperand(Src0Idx); runOnMachineFunction() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp107 computeKnownBitsMin(Register Src0,Register Src1,KnownBits & Known,const APInt & DemandedElts,unsigned Depth) computeKnownBitsMin() argument
601 computeNumSignBitsMin(Register Src0,Register Src1,const APInt & DemandedElts,unsigned Depth) computeNumSignBitsMin() argument
H A DCSEMIRBuilder.cpp242 const SrcOp &Src0 = SrcOps[0]; buildInstr() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp53 Register Dest0, Register Dest1, Register Src0, in PairedCopy() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp148 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedLoad() local
410 Value *Src0 = CI->getArgOperand(3); in scalarizeMaskedGather() local
H A DInferAddressSpaces.cpp928 Value *Src0 = Op.getOperand(1); updateAddressSpace() local
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp494 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitUnaryMaybeConstrainedFPBuiltin() local
511 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitBinaryMaybeConstrainedFPBuiltin() local
528 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitBinaryExpMaybeConstrainedFPBuiltin() local
548 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitTernaryMaybeConstrainedFPBuiltin() local
586 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitUnaryBuiltin() local
596 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitBinaryBuiltin() local
607 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitTernaryBuiltin() local
619 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitFPIntBuiltin() local
632 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitMaybeConstrainedFPToIntRoundBuiltin() local
648 llvm::Value *Src0 = CGF.EmitScalarExpr(E->getArg(0)); emitFrexpBuiltin() local
3473 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitBuiltinExpr() local
17897 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
17969 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
17978 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
17990 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
17996 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18022 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18033 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18053 Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18072 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
18533 llvm::Value *Src0 = EmitScalarExpr(E->getArg(0)); EmitAMDGPUBuiltinExpr() local
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4564 __anonf1bc66800602(Value *&Ptr, Value *&Mask, Value *&Src0, MaybeAlign &Alignment) visitMaskedStore() argument
4565 __anonf1bc66800702(Value *&Ptr, Value *&Mask, Value *&Src0, MaybeAlign &Alignment) visitMaskedStore() argument
4581 SDValue Src0 = getValue(Src0Operand); visitMaskedStore() local
4677 SDValue Src0 = getValue(I.getArgOperand(0)); visitMaskedScatter() local
4730 __anonf1bc66800802(Value *&Ptr, Value *&Mask, Value *&Src0, MaybeAlign &Alignment) visitMaskedLoad() argument
4731 __anonf1bc66800902(Value *&Ptr, Value *&Mask, Value *&Src0, MaybeAlign &Alignment) visitMaskedLoad() argument
4747 SDValue Src0 = getValue(Src0Operand); visitMaskedLoad() local
4781 SDValue Src0 = getValue(I.getArgOperand(3)); visitMaskedGather() local
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