Lines Matching defs:Src0

95   // Try to fold Src0
96   MachineOperand &Src0 = MI.getOperand(Src0Idx);
97   if (Src0.isReg()) {
98     Register Reg = Src0.getReg();
107             Src0.ChangeToImmediate(MovSrc.getImm());
110             Src0.ChangeToFrameIndex(MovSrc.getIndex());
113             Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(),
243   const MachineOperand &Src0 = MI.getOperand(0);
244   if (!Src0.isReg())
418   MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0);
429     else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg()))
458     else if (Src0.isImm() && !TII->isInlineConstant(Src0))
490     // Swap Src0 and Src1 by building a new instruction.
494         .add(Src0)
512   MachineOperand *Src0 = &MI.getOperand(1);
514   MachineOperand *SrcReg = Src0;
562         Src0->ChangeToImmediate(NewImm);
847         MachineOperand *Src0 = &MI.getOperand(1);
850         if (!Src0->isReg() && Src1->isReg()) {
852             std::swap(Src0, Src1);
858         if (Dest->getReg().isVirtual() && Src0->isReg()) {
859           MRI->setRegAllocationHint(Dest->getReg(), 0, Src0->getReg());
860           MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
864         if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {