Lines Matching defs:Src0
2719 MachineOperand &Src0,
2787 MachineOperand &Src0 = MI.getOperand(Src0Idx);
2791 if (Src0.isReg() && Src1.isReg()) {
2792 if (isOperandLegal(MI, Src1Idx, &Src0)) {
2798 } else if (Src0.isReg() && !Src1.isReg()) {
2801 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2802 } else if (!Src0.isReg() && Src1.isReg()) {
2803 if (isOperandLegal(MI, Src1Idx, &Src0))
2804 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2811 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
3511 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
3514 if (isInlineConstant(UseMI, *Src0, *ImmOp))
3527 if ((Src0->isReg() && Src0->getReg() == Reg) ||
3530 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1;
3567 const int64_t Imm = getImmFor(RegSrc == Src1 ? *Src0 : *Src1);
3574 Src0->setReg(SrcReg);
3575 Src0->setSubReg(SrcSubReg);
3576 Src0->setIsKill(RegSrc->isKill());
3602 if (Src0->isReg()) {
3606 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
3609 MRI->hasOneUse(Src0->getReg())) {
3610 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3613 RI.isSGPRReg(*MRI, Src0->getReg())) {
3616 // VGPR is okay as Src0 - fallthrough
3625 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
3916 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3917 if (!Src0->isReg() && !Src0->isImm())
3920 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
3929 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
3945 (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
3946 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
3972 .add(*Src0)
3992 .add(*Src0)
4003 if (Src0Literal || getFoldableImm(Src0, Imm, &DefMI)) {
4005 Imm = Src0->getImm();
4047 .add(*Src0)
5004 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5007 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
5008 if (!compareMachineOp(Src0, Src1) &&
5009 !compareMachineOp(Src0, Src2)) {
5026 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5029 if (!Src0.isReg() && !Src1.isReg() &&
5030 !isInlineConstant(Src0, Desc.operands()[Src0Idx]) &&
5032 !Src0.isIdenticalTo(Src1)) {
5095 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
5099 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
5854 MachineOperand &Src0 = MI.getOperand(Src0Idx);
5862 if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 && Src0.isReg() &&
5863 RI.isSGPRReg(MRI, Src0.getReg()))
5871 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
5874 .add(Src0);
5875 Src0.ChangeToRegister(Reg, false);
5888 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
5934 !isLegalRegOperand(MRI, InstrDesc.operands()[Src1Idx], Src0)) {
5947 Register Src0Reg = Src0.getReg();
5948 unsigned Src0SubReg = Src0.getSubReg();
5949 bool Src0Kill = Src0.isKill();
5952 Src0.ChangeToImmediate(Src1.getImm());
5954 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
5955 Src0.setSubReg(Src1.getSubReg());
6671 Register Src0 = MI.getOperand(1).getReg();
6673 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
6759 MachineOperand &Src0 = MI.getOperand(Src0Idx);
6761 .add(Src0);
6762 Src0.ChangeToRegister(Reg, false);
7226 MachineOperand &Src0 = Inst.getOperand(2);
7237 .add(Src0)
7551 MachineOperand &Src0 = Inst.getOperand(1);
7562 if (!IsSCC && Src0.isImm() && (Src0.getImm() == -1) && Src1.isImm() &&
7611 .add(Src0) // True
7617 .add(Src0) // True
7660 MachineOperand &Src0 = Inst.getOperand(1);
7665 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
7669 .add(Src0)
7679 bool Src0IsSGPR = Src0.isReg() &&
7680 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
7691 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
7698 .add(Src0)
7702 .add(Src0)
7726 MachineOperand &Src0 = Inst.getOperand(1);
7733 .add(Src0)
7755 MachineOperand &Src0 = Inst.getOperand(1);
7765 .add(Src0)
7782 MachineOperand &Src0 = Inst.getOperand(1);
7788 const TargetRegisterClass *Src0RC = Src0.isReg() ?
7789 MRI.getRegClass(Src0.getReg()) :
7795 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
7806 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
7847 MachineOperand &Src0 = Inst.getOperand(1);
7852 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
7866 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
7870 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
7956 MachineOperand &Src0 = Inst.getOperand(1);
7961 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
7975 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8015 MachineOperand &Src0 = Inst.getOperand(1);
8022 const TargetRegisterClass *Src0RC = Src0.isReg() ?
8023 MRI.getRegClass(Src0.getReg()) :
8035 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8039 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8082 MachineOperand &Src0 = Inst.getOperand(1);
8095 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
8096 Op0 = &Src0;
8100 Op1 = &Src0;
8312 MachineOperand &Src0 = Inst.getOperand(1);
8328 .add(Src0);
8342 .add(Src0)
8350 .add(Src0);
8362 .add(Src0);