Lines Matching defs:Src0
4975 MachineOperand &Src0 = MI.getOperand(2);
4981 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
4998 MachineOperand &Src0 = MI.getOperand(1);
5004 .add(Src0)
5014 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
5016 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
5050 MachineOperand &Src0 = MI.getOperand(1);
5056 .add(Src0)
5072 const TargetRegisterClass *Src0RC = Src0.isReg()
5073 ? MRI.getRegClass(Src0.getReg())
5085 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
5090 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
5132 MachineOperand &Src0 = MI.getOperand(2);
5138 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
5141 .addReg(Src0.getReg());
5142 Src0.setReg(RegOp0);
5189 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
5289 const MachineOperand &Src0 = MI.getOperand(1);
5299 const TargetRegisterClass *Src0RC = Src0.isReg()
5300 ? MRI.getRegClass(Src0.getReg())
5312 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
5317 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
6055 SDValue Src0 = N->getOperand(1);
6057 EVT CmpVT = Src0.getValueType();
6061 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
6069 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
6123 auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1,
6141 Operands.push_back(Src0);
6160 SDValue Src0 = N->getOperand(1);
6176 Src0 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src0) : Src0,
6189 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, MVT::i32);
6242 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT());
6252 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0,
6278 Src0 = DAG.getBitcast(VecVT, Src0);
6286 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VecVT);
6312 SDValue Src0 = N->getOperand(1);
6316 Src0, Src1);
6324 SDValue Src0 = N->getOperand(1);
6340 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
6342 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
8616 SDValue Src0 = Param->isAllOnes() ? Numerator : Denominator;
8618 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
9497 SDValue Src0 = Op.getOperand(4);
9500 if (isTypeLegal(Src0.getValueType()))
9507 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src0), // src0
10573 SDValue Src0 = Op.getOperand(0);
10576 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
10585 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
13275 SDValue Src0 = N->getOperand(0);
13279 if (isClampZeroToOne(Src0, Src1)) {
13294 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13295 std::swap(Src0, Src1);
13300 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13301 std::swap(Src0, Src1);
13304 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0);
13312 SDValue Src0 = N->getOperand(0);
13314 if (Src0.isUndef() && Src1.isUndef())
13816 static void placeSources(ByteProvider<SDValue> &Src0,
13821 assert(Src0.Src.has_value() && Src1.Src.has_value());
13824 Src0s.push_back({*Src0.Src, ((Src0.SrcOffset % 4) << 24) + 0x0c0c0c,
13825 Src0.SrcOffset / 4});
13832 std::pair<ByteProvider<SDValue>, ByteProvider<SDValue>> BPP = {Src0, Src1};
13834 BPP = {Src1, Src0};
13877 // for either Src0 or Src1, so just place them arbitrarily.
13883 {*Src0.Src,
13884 ((Src0.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
13978 checkDot4MulSignedness(const SDValue &N, ByteProvider<SDValue> &Src0,
14073 auto Src0 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0));
14074 if (!Src0)
14081 TempNode->getOperand(MulIdx), *Src0, *Src1,
14090 placeSources(*Src0, *Src1, Src0s, Src1s, I);
14096 auto Src0 =
14098 if (!Src0)
14105 TempNode->getOperand(AddIdx), *Src0, *Src1,
14113 placeSources(*Src0, *Src1, Src0s, Src1s, I + 1);
14139 SDValue Src0, Src1;
14174 Src0 = DAG.getBitcastedAnyExtOrTrunc(FirstEltOp, SL,
14182 Src0 = resolveSources(DAG, SL, Src0s, false, true);
14195 auto Dot = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SL, MVT::i32, IID, Src0,
15064 SDValue Src0 = Node->getOperand(1);
15068 if ((Src0.isMachineOpcode() &&
15069 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
15070 (Src0 == Src1 || Src0 == Src2))
15073 MVT VT = Src0.getValueType().getSimpleVT();
15075 getRegClassFor(VT, Src0.getNode()->isDivergent());
15081 UndefReg, Src0, SDValue());
15085 if (Src0.isMachineOpcode() &&
15086 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
15089 Src0 = Src1;
15092 Src0 = Src2;
15095 Src0 = UndefReg;
15102 Ops[1] = Src0;
15829 auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs();
15842 KB.computeKnownBitsImpl(Src0, Known0, DemandedElts, Depth + 1);