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Searched defs:SDValue (Results 1 – 15 of 15) sorted by relevance

/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSelectionDAGInfo.cpp21 SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, Align /*Alignment*/, in EmitTargetCodeForMemcpy() argument
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp86 EmitCopyFromReg(SDNode * Node,unsigned ResNo,bool IsClone,Register SrcReg,DenseMap<SDValue,Register> & VRBaseMap) EmitCopyFromReg() argument
190 CreateVirtualRegisters(SDNode * Node,MachineInstrBuilder & MIB,const MCInstrDesc & II,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap) CreateVirtualRegisters() argument
269 getVR(SDValue Op,DenseMap<SDValue,Register> & VRBaseMap) getVR() argument
321 AddRegisterOperand(MachineInstrBuilder & MIB,SDValue Op,unsigned IIOpNum,const MCInstrDesc * II,DenseMap<SDValue,Register> & VRBaseMap,bool IsDebug,bool IsClone,bool IsCloned) AddRegisterOperand() argument
402 AddOperand(MachineInstrBuilder & MIB,SDValue Op,unsigned IIOpNum,const MCInstrDesc * II,DenseMap<SDValue,Register> & VRBaseMap,bool IsDebug,bool IsClone,bool IsCloned) AddOperand() argument
503 EmitSubregNode(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap,bool IsClone,bool IsCloned) EmitSubregNode() argument
637 EmitCopyToRegClassNode(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap) EmitCopyToRegClassNode() argument
657 EmitRegSequence(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap,bool IsClone,bool IsCloned) EmitRegSequence() argument
706 EmitDbgValue(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap) EmitDbgValue() argument
758 AddDbgValueLocationOps(MachineInstrBuilder & MIB,const MCInstrDesc & DbgValDesc,ArrayRef<SDDbgOperand> LocationOps,DenseMap<SDValue,Register> & VRBaseMap) AddDbgValueLocationOps() argument
789 EmitDbgInstrRef(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap) EmitDbgInstrRef() argument
931 EmitDbgValueList(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap) EmitDbgValueList() argument
947 EmitDbgValueFromSingleOp(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap) EmitDbgValueFromSingleOp() argument
999 EmitMachineNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap) EmitMachineNode() argument
1241 EmitSpecialNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap) EmitSpecialNode() argument
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H A DInstrEmitter.h143 EmitNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap) EmitNode() argument
H A DScheduleDAGSDNodes.cpp740 ProcessSDDbgValues(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,DenseMap<SDValue,Register> & VRBaseMap,unsigned Order) ProcessSDDbgValues() argument
785 ProcessSourceNode(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,DenseMap<SDValue,Register> & VRBaseMap,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,SmallSet<Register,8> & Seen,MachineInstr * NewInsn) ProcessSourceNode() argument
864 __anonc569a2d10302(SDNode *Node, bool IsClone, bool IsCloned, DenseMap<SDValue, Register> &VRBaseMap) EmitSchedule() argument
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H A DSelectionDAGISel.cpp2803 CheckSame(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes) CheckSame() argument
2813 CheckChildSame(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes,unsigned ChildNo) CheckChildSame() argument
2969 IsPredicateKnownToFail(const unsigned char * Table,unsigned Index,SDValue N,bool & Result,const SelectionDAGISel & SDISel,SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes) IsPredicateKnownToFail() argument
3142 MatchStateUpdater(SelectionDAG & DAG,SDNode ** NodeToMatch,SmallVectorImpl<std::pair<SDValue,SDNode * >> & RN,SmallVectorImpl<MatchScope> & MS) MatchStateUpdater() argument
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H A DStatepointLowering.cpp524 lowerStatepointMetaArgs(SmallVectorImpl<SDValue> & Ops,SmallVectorImpl<MachineMemOperand * > & MemRefs,SmallVectorImpl<SDValue> & GCPtrs,DenseMap<SDValue,int> & LowerAsVReg,SelectionDAGBuilder::StatepointLoweringInfo & SI,SelectionDAGBuilder & Builder) lowerStatepointMetaArgs() argument
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H A DSelectionDAG.cpp7744 chainLoadsAndStoresForMemcpy(SelectionDAG & DAG,const SDLoc & dl,SmallVector<SDValue,32> & OutChains,unsigned From,unsigned To,SmallVector<SDValue,16> & OutLoadChains,SmallVector<SDValue,16> & OutStoreChains) chainLoadsAndStoresForMemcpy() argument
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/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3816 getPreIndexedAddressParts(SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &) getPreIndexedAddressParts() argument
3827 getPostIndexedAddressParts(SDNode *,SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &) getPostIndexedAddressParts() argument
4363 IsDesirableToPromoteOp(SDValue,EVT &) IsDesirableToPromoteOp() argument
4489 LowerFormalArguments(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::InputArg> &,const SDLoc &,SelectionDAG &,SmallVectorImpl<SDValue> &) LowerFormalArguments() argument
4492 LowerFormalArguments(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::InputArg> &,const SDLoc &,SelectionDAG &,SmallVectorImpl<SDValue> &) LowerFormalArguments() argument
4750 LowerCall(CallLoweringInfo &,SmallVectorImpl<SDValue> &) LowerCall() argument
4772 LowerReturn(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::OutputArg> &,const SmallVectorImpl<SDValue> &,const SDLoc &,SelectionDAG &) LowerReturn() argument
4775 LowerReturn(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::OutputArg> &,const SmallVectorImpl<SDValue> &,const SDLoc &,SelectionDAG &) LowerReturn() argument
4786 isUsedByReturnOnly(SDNode *,SDValue &) isUsedByReturnOnly() argument
4894 ReplaceNodeResults(SDNode *,SmallVectorImpl<SDValue> &,SelectionDAG &) ReplaceNodeResults() argument
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H A DSelectionDAGISel.h30 class SDValue; global() variable
436 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result) CheckComplexPattern() argument
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h818 hasAndNotCompare(SDValue) hasAndNotCompare() argument
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H A DPPCISelLowering.cpp5710 buildCallOperands(SmallVectorImpl<SDValue> & Ops,PPCTargetLowering::CallFlags CFlags,const SDLoc & dl,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue Glue,SDValue Chain,SDValue & Callee,int SPDiff,const PPCSubtarget & Subtarget) buildCallOperands() argument
5794 FinishCall(CallFlags CFlags,const SDLoc & dl,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue Glue,SDValue Chain,SDValue CallSeqStart,SDValue & Callee,int SPDiff,unsigned NumBytes,const SmallVectorImpl<ISD::InputArg> & Ins,SmallVectorImpl<SDValue> & InVals,const CallBase * CB) const FinishCall() argument
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/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp2237 pickOpcodeForVectorStParam(SmallVector<SDValue,8> & Ops,unsigned NumElts,MVT::SimpleValueType MemTy,SelectionDAG * CurDAG,SDLoc DL) pickOpcodeForVectorStParam() argument
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/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1455 shouldScalarizeBinop(SDValue) shouldScalarizeBinop() argument
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H A DX86ISelLowering.cpp22814 optimizeFMulOrFDivAsShiftAddBitcast(SDNode * N,SDValue,SDValue IntPow2) const optimizeFMulOrFDivAsShiftAddBitcast() argument
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10119 isOrXorChain(SDValue N,unsigned & Num,SmallVector<std::pair<SDValue,SDValue>,16> & WorkList) isOrXorChain() argument
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