1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the SelectionDAGISel class, which is used as the common 10 // base class for SelectionDAG-based instruction selectors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 16 17 #include "llvm/Analysis/AliasAnalysis.h" 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/MachinePassManager.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/IR/BasicBlock.h" 22 #include <memory> 23 24 namespace llvm { 25 class AAResults; 26 class AssumptionCache; 27 class TargetInstrInfo; 28 class TargetMachine; 29 class SSPLayoutInfo; 30 class SelectionDAGBuilder; 31 class SDValue; 32 class MachineRegisterInfo; 33 class MachineFunction; 34 class OptimizationRemarkEmitter; 35 class TargetLowering; 36 class TargetLibraryInfo; 37 class TargetTransformInfo; 38 class FunctionLoweringInfo; 39 class SwiftErrorValueTracking; 40 class GCFunctionInfo; 41 class ScheduleDAGSDNodes; 42 43 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 44 /// pattern-matching instruction selectors. 45 class SelectionDAGISel { 46 public: 47 TargetMachine &TM; 48 const TargetLibraryInfo *LibInfo; 49 std::unique_ptr<FunctionLoweringInfo> FuncInfo; 50 SwiftErrorValueTracking *SwiftError; 51 MachineFunction *MF; 52 MachineModuleInfo *MMI; 53 MachineRegisterInfo *RegInfo; 54 SelectionDAG *CurDAG; 55 std::unique_ptr<SelectionDAGBuilder> SDB; 56 mutable std::optional<BatchAAResults> BatchAA; 57 AssumptionCache *AC = nullptr; 58 GCFunctionInfo *GFI = nullptr; 59 SSPLayoutInfo *SP = nullptr; 60 #if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS 61 TargetTransformInfo *TTI = nullptr; 62 #endif 63 CodeGenOptLevel OptLevel; 64 const TargetInstrInfo *TII; 65 const TargetLowering *TLI; 66 bool FastISelFailed; 67 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 68 69 /// Current optimization remark emitter. 70 /// Used to report things like combines and FastISel failures. 71 std::unique_ptr<OptimizationRemarkEmitter> ORE; 72 73 /// True if the function currently processing is in the function printing list 74 /// (i.e. `-filter-print-funcs`). 75 /// This is primarily used by ISEL_DUMP, which spans in multiple member 76 /// functions. Storing the filter result here so that we only need to do the 77 /// filtering once. 78 bool MatchFilterFuncName = false; 79 StringRef FuncName; 80 81 explicit SelectionDAGISel(TargetMachine &tm, 82 CodeGenOptLevel OL = CodeGenOptLevel::Default); 83 virtual ~SelectionDAGISel(); 84 85 /// Returns a (possibly null) pointer to the current BatchAAResults. 86 BatchAAResults *getBatchAA() const { 87 if (BatchAA.has_value()) 88 return &BatchAA.value(); 89 return nullptr; 90 } 91 92 const TargetLowering *getTargetLowering() const { return TLI; } 93 94 void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM); 95 void initializeAnalysisResults(MachineFunctionPass &MFP); 96 97 virtual bool runOnMachineFunction(MachineFunction &mf); 98 99 virtual void emitFunctionEntryCode() {} 100 101 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 102 /// instruction selection starts. 103 virtual void PreprocessISelDAG() {} 104 105 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 106 /// right after selection. 107 virtual void PostprocessISelDAG() {} 108 109 /// Main hook for targets to transform nodes into machine nodes. 110 virtual void Select(SDNode *N) = 0; 111 112 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 113 /// addressing mode, according to the specified constraint. If this does 114 /// not match or is not implemented, return true. The resultant operands 115 /// (which will appear in the machine instruction) should be added to the 116 /// OutOps vector. 117 virtual bool 118 SelectInlineAsmMemoryOperand(const SDValue &Op, 119 InlineAsm::ConstraintCode ConstraintID, 120 std::vector<SDValue> &OutOps) { 121 return true; 122 } 123 124 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 125 /// operand node N of U during instruction selection that starts at Root. 126 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 127 128 /// IsLegalToFold - Returns true if the specific operand node N of 129 /// U can be folded during instruction selection that starts at Root. 130 /// FIXME: This is a static member function because the MSP430/X86 131 /// targets, which uses it during isel. This could become a proper member. 132 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 133 CodeGenOptLevel OptLevel, 134 bool IgnoreChains = false); 135 136 static void InvalidateNodeId(SDNode *N); 137 static int getUninvalidatedNodeId(SDNode *N); 138 139 static void EnforceNodeIdInvariant(SDNode *N); 140 141 // Opcodes used by the DAG state machine: 142 enum BuiltinOpcodes { 143 OPC_Scope, 144 OPC_RecordNode, 145 OPC_RecordChild0, 146 OPC_RecordChild1, 147 OPC_RecordChild2, 148 OPC_RecordChild3, 149 OPC_RecordChild4, 150 OPC_RecordChild5, 151 OPC_RecordChild6, 152 OPC_RecordChild7, 153 OPC_RecordMemRef, 154 OPC_CaptureGlueInput, 155 OPC_MoveChild, 156 OPC_MoveChild0, 157 OPC_MoveChild1, 158 OPC_MoveChild2, 159 OPC_MoveChild3, 160 OPC_MoveChild4, 161 OPC_MoveChild5, 162 OPC_MoveChild6, 163 OPC_MoveChild7, 164 OPC_MoveSibling, 165 OPC_MoveSibling0, 166 OPC_MoveSibling1, 167 OPC_MoveSibling2, 168 OPC_MoveSibling3, 169 OPC_MoveSibling4, 170 OPC_MoveSibling5, 171 OPC_MoveSibling6, 172 OPC_MoveSibling7, 173 OPC_MoveParent, 174 OPC_CheckSame, 175 OPC_CheckChild0Same, 176 OPC_CheckChild1Same, 177 OPC_CheckChild2Same, 178 OPC_CheckChild3Same, 179 OPC_CheckPatternPredicate, 180 OPC_CheckPatternPredicate0, 181 OPC_CheckPatternPredicate1, 182 OPC_CheckPatternPredicate2, 183 OPC_CheckPatternPredicate3, 184 OPC_CheckPatternPredicate4, 185 OPC_CheckPatternPredicate5, 186 OPC_CheckPatternPredicate6, 187 OPC_CheckPatternPredicate7, 188 OPC_CheckPatternPredicateTwoByte, 189 OPC_CheckPredicate, 190 OPC_CheckPredicate0, 191 OPC_CheckPredicate1, 192 OPC_CheckPredicate2, 193 OPC_CheckPredicate3, 194 OPC_CheckPredicate4, 195 OPC_CheckPredicate5, 196 OPC_CheckPredicate6, 197 OPC_CheckPredicate7, 198 OPC_CheckPredicateWithOperands, 199 OPC_CheckOpcode, 200 OPC_SwitchOpcode, 201 OPC_CheckType, 202 // Space-optimized forms that implicitly encode VT. 203 OPC_CheckTypeI32, 204 OPC_CheckTypeI64, 205 OPC_CheckTypeRes, 206 OPC_SwitchType, 207 OPC_CheckChild0Type, 208 OPC_CheckChild1Type, 209 OPC_CheckChild2Type, 210 OPC_CheckChild3Type, 211 OPC_CheckChild4Type, 212 OPC_CheckChild5Type, 213 OPC_CheckChild6Type, 214 OPC_CheckChild7Type, 215 216 OPC_CheckChild0TypeI32, 217 OPC_CheckChild1TypeI32, 218 OPC_CheckChild2TypeI32, 219 OPC_CheckChild3TypeI32, 220 OPC_CheckChild4TypeI32, 221 OPC_CheckChild5TypeI32, 222 OPC_CheckChild6TypeI32, 223 OPC_CheckChild7TypeI32, 224 225 OPC_CheckChild0TypeI64, 226 OPC_CheckChild1TypeI64, 227 OPC_CheckChild2TypeI64, 228 OPC_CheckChild3TypeI64, 229 OPC_CheckChild4TypeI64, 230 OPC_CheckChild5TypeI64, 231 OPC_CheckChild6TypeI64, 232 OPC_CheckChild7TypeI64, 233 234 OPC_CheckInteger, 235 OPC_CheckChild0Integer, 236 OPC_CheckChild1Integer, 237 OPC_CheckChild2Integer, 238 OPC_CheckChild3Integer, 239 OPC_CheckChild4Integer, 240 OPC_CheckCondCode, 241 OPC_CheckChild2CondCode, 242 OPC_CheckValueType, 243 OPC_CheckComplexPat, 244 OPC_CheckComplexPat0, 245 OPC_CheckComplexPat1, 246 OPC_CheckComplexPat2, 247 OPC_CheckComplexPat3, 248 OPC_CheckComplexPat4, 249 OPC_CheckComplexPat5, 250 OPC_CheckComplexPat6, 251 OPC_CheckComplexPat7, 252 OPC_CheckAndImm, 253 OPC_CheckOrImm, 254 OPC_CheckImmAllOnesV, 255 OPC_CheckImmAllZerosV, 256 OPC_CheckFoldableChainNode, 257 258 OPC_EmitInteger, 259 // Space-optimized forms that implicitly encode integer VT. 260 OPC_EmitInteger8, 261 OPC_EmitInteger16, 262 OPC_EmitInteger32, 263 OPC_EmitInteger64, 264 OPC_EmitStringInteger, 265 // Space-optimized forms that implicitly encode integer VT. 266 OPC_EmitStringInteger32, 267 OPC_EmitRegister, 268 OPC_EmitRegisterI32, 269 OPC_EmitRegisterI64, 270 OPC_EmitRegister2, 271 OPC_EmitConvertToTarget, 272 OPC_EmitConvertToTarget0, 273 OPC_EmitConvertToTarget1, 274 OPC_EmitConvertToTarget2, 275 OPC_EmitConvertToTarget3, 276 OPC_EmitConvertToTarget4, 277 OPC_EmitConvertToTarget5, 278 OPC_EmitConvertToTarget6, 279 OPC_EmitConvertToTarget7, 280 OPC_EmitMergeInputChains, 281 OPC_EmitMergeInputChains1_0, 282 OPC_EmitMergeInputChains1_1, 283 OPC_EmitMergeInputChains1_2, 284 OPC_EmitCopyToReg, 285 OPC_EmitCopyToReg0, 286 OPC_EmitCopyToReg1, 287 OPC_EmitCopyToReg2, 288 OPC_EmitCopyToReg3, 289 OPC_EmitCopyToReg4, 290 OPC_EmitCopyToReg5, 291 OPC_EmitCopyToReg6, 292 OPC_EmitCopyToReg7, 293 OPC_EmitCopyToRegTwoByte, 294 OPC_EmitNodeXForm, 295 OPC_EmitNode, 296 // Space-optimized forms that implicitly encode number of result VTs. 297 OPC_EmitNode0, 298 OPC_EmitNode1, 299 OPC_EmitNode2, 300 // Space-optimized forms that implicitly encode EmitNodeInfo. 301 OPC_EmitNode0None, 302 OPC_EmitNode1None, 303 OPC_EmitNode2None, 304 OPC_EmitNode0Chain, 305 OPC_EmitNode1Chain, 306 OPC_EmitNode2Chain, 307 OPC_MorphNodeTo, 308 // Space-optimized forms that implicitly encode number of result VTs. 309 OPC_MorphNodeTo0, 310 OPC_MorphNodeTo1, 311 OPC_MorphNodeTo2, 312 // Space-optimized forms that implicitly encode EmitNodeInfo. 313 OPC_MorphNodeTo0None, 314 OPC_MorphNodeTo1None, 315 OPC_MorphNodeTo2None, 316 OPC_MorphNodeTo0Chain, 317 OPC_MorphNodeTo1Chain, 318 OPC_MorphNodeTo2Chain, 319 OPC_MorphNodeTo0GlueInput, 320 OPC_MorphNodeTo1GlueInput, 321 OPC_MorphNodeTo2GlueInput, 322 OPC_MorphNodeTo0GlueOutput, 323 OPC_MorphNodeTo1GlueOutput, 324 OPC_MorphNodeTo2GlueOutput, 325 OPC_CompleteMatch, 326 // Contains 32-bit offset in table for pattern being selected 327 OPC_Coverage 328 }; 329 330 enum { 331 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 332 OPFL_Chain = 1, // Node has a chain input. 333 OPFL_GlueInput = 2, // Node has a glue input. 334 OPFL_GlueOutput = 4, // Node has a glue output. 335 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 336 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 337 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 338 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 339 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 340 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 341 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 342 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 343 344 OPFL_VariadicInfo = OPFL_Variadic6 345 }; 346 347 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 348 /// number of fixed arity values that should be skipped when copying from the 349 /// root. 350 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 351 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 352 } 353 354 355 protected: 356 /// DAGSize - Size of DAG being instruction selected. 357 /// 358 unsigned DAGSize = 0; 359 360 /// ReplaceUses - replace all uses of the old node F with the use 361 /// of the new node T. 362 void ReplaceUses(SDValue F, SDValue T) { 363 CurDAG->ReplaceAllUsesOfValueWith(F, T); 364 EnforceNodeIdInvariant(T.getNode()); 365 } 366 367 /// ReplaceUses - replace all uses of the old nodes F with the use 368 /// of the new nodes T. 369 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 370 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 371 for (unsigned i = 0; i < Num; ++i) 372 EnforceNodeIdInvariant(T[i].getNode()); 373 } 374 375 /// ReplaceUses - replace all uses of the old node F with the use 376 /// of the new node T. 377 void ReplaceUses(SDNode *F, SDNode *T) { 378 CurDAG->ReplaceAllUsesWith(F, T); 379 EnforceNodeIdInvariant(T); 380 } 381 382 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. 383 void ReplaceNode(SDNode *F, SDNode *T) { 384 CurDAG->ReplaceAllUsesWith(F, T); 385 EnforceNodeIdInvariant(T); 386 CurDAG->RemoveDeadNode(F); 387 } 388 389 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 390 /// by tblgen. Others should not call it. 391 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 392 const SDLoc &DL); 393 394 /// getPatternForIndex - Patterns selected by tablegen during ISEL 395 virtual StringRef getPatternForIndex(unsigned index) { 396 llvm_unreachable("Tblgen should generate the implementation of this!"); 397 } 398 399 /// getIncludePathForIndex - get the td source location of pattern instantiation 400 virtual StringRef getIncludePathForIndex(unsigned index) { 401 llvm_unreachable("Tblgen should generate the implementation of this!"); 402 } 403 404 bool shouldOptForSize(const MachineFunction *MF) const { 405 return CurDAG->shouldOptForSize(); 406 } 407 408 public: 409 // Calls to these predicates are generated by tblgen. 410 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 411 int64_t DesiredMaskS) const; 412 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 413 int64_t DesiredMaskS) const; 414 415 416 /// CheckPatternPredicate - This function is generated by tblgen in the 417 /// target. It runs the specified pattern predicate and returns true if it 418 /// succeeds or false if it fails. The number is a private implementation 419 /// detail to the code tblgen produces. 420 virtual bool CheckPatternPredicate(unsigned PredNo) const { 421 llvm_unreachable("Tblgen should generate the implementation of this!"); 422 } 423 424 /// CheckNodePredicate - This function is generated by tblgen in the target. 425 /// It runs node predicate number PredNo and returns true if it succeeds or 426 /// false if it fails. The number is a private implementation 427 /// detail to the code tblgen produces. 428 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 429 llvm_unreachable("Tblgen should generate the implementation of this!"); 430 } 431 432 /// CheckNodePredicateWithOperands - This function is generated by tblgen in 433 /// the target. 434 /// It runs node predicate number PredNo and returns true if it succeeds or 435 /// false if it fails. The number is a private implementation detail to the 436 /// code tblgen produces. 437 virtual bool CheckNodePredicateWithOperands( 438 SDNode *N, unsigned PredNo, 439 const SmallVectorImpl<SDValue> &Operands) const { 440 llvm_unreachable("Tblgen should generate the implementation of this!"); 441 } 442 443 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 444 unsigned PatternNo, 445 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 446 llvm_unreachable("Tblgen should generate the implementation of this!"); 447 } 448 449 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 450 llvm_unreachable("Tblgen should generate this!"); 451 } 452 453 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 454 unsigned TableSize); 455 456 /// Return true if complex patterns for this target can mutate the 457 /// DAG. 458 virtual bool ComplexPatternFuncMutatesDAG() const { 459 return false; 460 } 461 462 /// Return whether the node may raise an FP exception. 463 bool mayRaiseFPException(SDNode *Node) const; 464 465 bool isOrEquivalentToAdd(const SDNode *N) const; 466 467 private: 468 469 // Calls to these functions are generated by tblgen. 470 void Select_INLINEASM(SDNode *N); 471 void Select_READ_REGISTER(SDNode *Op); 472 void Select_WRITE_REGISTER(SDNode *Op); 473 void Select_UNDEF(SDNode *N); 474 void Select_FAKE_USE(SDNode *N); 475 void CannotYetSelect(SDNode *N); 476 477 void Select_FREEZE(SDNode *N); 478 void Select_ARITH_FENCE(SDNode *N); 479 void Select_MEMBARRIER(SDNode *N); 480 481 void Select_CONVERGENCECTRL_ANCHOR(SDNode *N); 482 void Select_CONVERGENCECTRL_ENTRY(SDNode *N); 483 void Select_CONVERGENCECTRL_LOOP(SDNode *N); 484 485 void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand, 486 SDLoc DL); 487 void Select_STACKMAP(SDNode *N); 488 void Select_PATCHPOINT(SDNode *N); 489 490 void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N); 491 492 private: 493 void DoInstructionSelection(); 494 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 495 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 496 497 /// Prepares the landing pad to take incoming values or do other EH 498 /// personality specific tasks. Returns true if the block should be 499 /// instruction selected, false if no code should be emitted for it. 500 bool PrepareEHLandingPad(); 501 502 // Mark and Report IPToState for each Block under AsynchEH 503 void reportIPToStateForBlocks(MachineFunction *Fn); 504 505 /// Perform instruction selection on all basic blocks in the function. 506 void SelectAllBasicBlocks(const Function &Fn); 507 508 /// Perform instruction selection on a single basic block, for 509 /// instructions between \p Begin and \p End. \p HadTailCall will be set 510 /// to true if a call in the block was translated as a tail call. 511 void SelectBasicBlock(BasicBlock::const_iterator Begin, 512 BasicBlock::const_iterator End, 513 bool &HadTailCall); 514 void FinishBasicBlock(); 515 516 void CodeGenAndEmitDAG(); 517 518 /// Generate instructions for lowering the incoming arguments of the 519 /// given function. 520 void LowerArguments(const Function &F); 521 522 void ComputeLiveOutVRegInfo(); 523 524 /// Create the scheduler. If a specific scheduler was specified 525 /// via the SchedulerRegistry, use it, otherwise select the 526 /// one preferred by the target. 527 /// 528 ScheduleDAGSDNodes *CreateScheduler(); 529 530 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 531 /// state machines that start with a OPC_SwitchOpcode node. 532 std::vector<unsigned> OpcodeOffset; 533 534 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 535 SmallVectorImpl<SDNode *> &ChainNodesMatched, 536 bool isMorphNodeTo); 537 }; 538 539 class SelectionDAGISelLegacy : public MachineFunctionPass { 540 std::unique_ptr<SelectionDAGISel> Selector; 541 542 public: 543 SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S); 544 545 ~SelectionDAGISelLegacy() override = default; 546 547 void getAnalysisUsage(AnalysisUsage &AU) const override; 548 549 bool runOnMachineFunction(MachineFunction &MF) override; 550 }; 551 552 class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> { 553 std::unique_ptr<SelectionDAGISel> Selector; 554 555 protected: 556 SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector) 557 : Selector(std::move(Selector)) {} 558 559 public: 560 PreservedAnalyses run(MachineFunction &MF, 561 MachineFunctionAnalysisManager &MFAM); 562 static bool isRequired() { return true; } 563 }; 564 } 565 566 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 567