Lines Matching defs:SDValue
159 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
1879 static bool isFloatingPointZero(SDValue Op) {
2548 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2549 SDValue OpVal;
2558 SDValue UniquedVals[4];
2565 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2570 return SDValue(); // no match.
2603 return SDValue();
2612 return SDValue();
2615 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2629 if (ValSizeInBytes < ByteSize) return SDValue();
2634 return SDValue();
2640 if (MaskVal == 0) return SDValue();
2645 return SDValue();
2666 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2675 static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2687 bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2688 SDValue &Index,
2712 bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2723 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2814 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2902 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2918 bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2919 SDValue &Base,
2967 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2968 SDValue &Index,
2997 template <typename Ty> static bool isValidPCRelNode(SDValue N) {
3005 bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
3048 SDValue LoadedVal(N, 0);
3064 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3065 SDValue &Offset,
3071 SDValue Ptr;
3107 SDValue Val = cast<StoreSDNode>(N)->getValue();
3164 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3168 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3170 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3171 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3192 SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3193 SDValue GA) const {
3195 SDValue Reg = Subtarget.isPPC64() ? DAG.getRegister(PPC::X2, VT)
3199 SDValue Ops[] = { GA, Reg };
3206 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3218 SDValue ConstPool = DAG.getTargetConstantPool(
3223 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3232 SDValue GA =
3237 SDValue CPIHi =
3239 SDValue CPILo =
3262 SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3293 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3301 SDValue GA =
3303 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3311 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3320 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3325 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3326 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3330 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3340 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3342 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3350 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3363 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3364 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3368 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3422 SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3448 SDValue VariableOffsetTGA =
3450 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3451 SDValue TLSReg;
3515 SDValue VariableOffsetTGA =
3517 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3525 SDValue ModuleHandleTGA =
3527 SDValue ModuleHandleTOC = getTOCEntry(DAG, dl, ModuleHandleTGA);
3528 SDValue ModuleHandle =
3556 SDValue VariableOffsetTGA =
3558 SDValue RegionHandleTGA =
3560 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3561 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3566 SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3588 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3589 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3591 SDValue MatAddr =
3596 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3598 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3600 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3603 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3609 SDValue TGA = DAG.getTargetGlobalAddress(
3611 SDValue TGATLS = DAG.getTargetGlobalAddress(
3613 SDValue TPOffset;
3615 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3619 SDValue GOTPtr;
3622 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3640 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3645 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3646 SDValue GOTPtr;
3649 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3664 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3666 SDValue MatPCRel =
3671 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3672 SDValue GOTPtr;
3675 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3684 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3686 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3694 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3707 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3709 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3710 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3714 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3720 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3729 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3735 SDValue GAHi =
3737 SDValue GALo =
3743 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3747 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3748 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3749 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3776 return SDValue();
3777 SDValue SetCC32 = DAG.getSetCC(
3781 SDValue Shuff =
3795 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3803 return SDValue();
3813 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3816 return SDValue();
3819 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3823 SDValue InChain = Node->getOperand(0);
3824 SDValue VAListPtr = Node->getOperand(1);
3831 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3837 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3839 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3841 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3849 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3853 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3857 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3860 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3864 SDValue OverflowArea =
3868 SDValue RegSaveArea =
3873 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3877 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3883 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3892 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3902 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3905 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3918 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3929 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3937 SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
3988 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3993 SDValue Chain = Op.getOperand(0);
3994 SDValue Trmp = Op.getOperand(1); // trampoline
3995 SDValue FPtr = Op.getOperand(2); // nested function
3996 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
4023 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
4027 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
4037 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4067 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
4068 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
4069 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
4071 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
4075 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
4078 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
4081 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
4086 SDValue firstStore =
4090 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
4094 SDValue secondStore =
4101 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
4230 SDValue PPCTargetLowering::LowerFormalArguments(
4231 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4233 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4245 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
4246 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4248 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4349 SDValue ArgValue;
4356 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
4357 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
4385 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4415 SmallVector<SDValue, 8> MemOps;
4447 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4458 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4459 SDValue Store =
4463 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4477 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
4478 SDValue Store =
4482 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
4496 SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
4498 SDValue ArgVal,
4510 SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4511 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4513 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4572 SmallVector<SDValue, 8> MemOps;
4576 SDValue ArgVal;
4628 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4645 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4651 SDValue Arg = FIN;
4653 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4661 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4663 SDValue Store =
4685 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4686 SDValue Addr = FIN;
4688 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4693 SDValue Store =
4829 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4862 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4870 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4871 SDValue Store =
4875 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
5185 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
5204 SDValue Arg;
5205 SDValue FrameIdxOp;
5215 SelectionDAG &DAG, SDValue Chain,
5217 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
5219 SDValue Arg = TailCallArgs[i].Arg;
5220 SDValue FIN = TailCallArgs[i].FrameIdxOp;
5231 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
5232 SDValue OldRetAddr, SDValue OldFP,
5243 SDValue NewRetAddrFrIdx =
5254 SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64, SDValue Arg,
5261 SDValue FIN = DAG.getFrameIndex(FI, VT);
5272 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5273 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5274 SDValue &FPOpOut, const SDLoc &dl) const {
5280 Chain = SDValue(LROpOut.getNode(), 1);
5291 static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5292 SDValue Chain, ISD::ArgFlagsTy Flags,
5294 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5303 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5304 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5305 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5310 SDValue StackPtr;
5327 PrepareTailCall(SelectionDAG &DAG, SDValue &InGlue, SDValue &Chain,
5328 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5329 SDValue FPOp,
5333 SmallVector<SDValue, 8> MemOpChains2;
5335 InGlue = SDValue();
5362 SDValue PPCTargetLowering::LowerCallResult(
5363 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
5365 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5380 SDValue Val;
5383 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5388 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5426 static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5457 const Function &Caller, const SDValue &Callee,
5519 static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5523 return SDValue(Dest, 0);
5598 static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5605 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5614 static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5615 SDValue &Glue, SDValue &Chain,
5617 SDValue MTCTROps[] = {Chain, Callee, Glue};
5625 static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5626 SDValue &Glue, SDValue &Chain,
5627 SDValue CallSeqStart,
5658 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5678 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5683 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5684 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5685 SDValue TOCPtr =
5690 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5691 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5692 SDValue LoadEnvPtr =
5698 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5707 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5718 buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5721 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5722 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5749 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5751 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5752 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5800 SDValue PPCTargetLowering::FinishCall(
5802 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5803 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5805 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5824 SmallVector<SDValue, 8> Ops;
5845 SDValue Ret = DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5909 SDValue
5911 SmallVectorImpl<SDValue> &InVals) const {
5915 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5917 SDValue Chain = CLI.Chain;
5918 SDValue Callee = CLI.Callee;
5942 // case the SDValue for the callee could be a load (to load the address
5987 SDValue PPCTargetLowering::LowerCall_32SVR4(
5988 SDValue Chain, SDValue Callee, CallFlags CFlags,
5990 const SmallVectorImpl<SDValue> &OutVals,
5992 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
6086 SDValue CallSeqStart = Chain;
6090 SDValue LROp, FPOp;
6096 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
6098 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
6100 SmallVector<SDValue, 8> MemOpChains;
6111 SDValue Arg = OutVals[RealArgIdx];
6126 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
6132 SDValue MemcpyCall =
6138 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
6163 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
6178 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
6197 SDValue InGlue;
6208 SDValue Ops[] = { Chain, InGlue };
6226 SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
6227 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
6229 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
6234 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
6241 SDValue PPCTargetLowering::LowerCall_64SVR4(
6242 SDValue Chain, SDValue Callee, CallFlags CFlags,
6244 const SmallVectorImpl<SDValue> &OutVals,
6246 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
6414 SDValue CallSeqStart = Chain;
6418 SDValue LROp, FPOp;
6424 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
6432 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
6435 SmallVector<SDValue, 8> MemOpChains;
6437 SDValue Arg = OutVals[i];
6444 SDValue PtrOff;
6498 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
6509 SDValue AddPtr = PtrOff;
6511 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
6542 SDValue AddPtr = PtrOff;
6544 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
6552 SDValue Load =
6565 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
6566 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
6570 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, AddArg,
6643 SDValue ArgVal;
6657 SDValue Lo, Hi;
6675 ArgVal = SDValue();
6687 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
6731 SDValue Store =
6735 SDValue Load =
6744 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
6746 SDValue Load =
6793 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
6796 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
6797 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
6811 SDValue InGlue;
7130 static SDValue truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT,
7131 SelectionDAG &DAG, SDValue ArgValue,
7204 SDValue PPCTargetLowering::LowerFormalArguments_AIX(
7205 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
7207 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
7239 SmallVector<SDValue, 8> MemOps;
7264 SDValue Parm = DAG.getCopyFromReg(Chain, dl, VReg, SaveVT);
7266 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
7267 SDValue StoreReg = DAG.getStore(Chain, dl, Parm, FIN,
7293 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
7294 SDValue ArgValue =
7304 SDValue ArgValueTrunc = DAG.getNode(
7307 SDValue ArgValueExt =
7404 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
7420 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
7433 SDValue CopyFrom = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
7439 SDValue Store = DAG.getStore(
7478 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
7510 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
7530 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
7531 SDValue Store =
7535 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
7546 SDValue PPCTargetLowering::LowerCall_AIX(
7547 SDValue Chain, SDValue Callee, CallFlags CFlags,
7549 const SmallVectorImpl<SDValue> &OutVals,
7551 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
7595 SDValue CallSeqStart = Chain;
7597 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
7598 SmallVector<SDValue, 8> MemOpChains;
7603 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64)
7608 SDValue Arg = OutVals[ValNo];
7633 SDValue Load = GetLoad(PtrVT, LoadOffset);
7673 SDValue ResidueVal;
7679 SDValue Load = GetLoad(VT, LoadOffset);
7693 SDValue SHLAmt = DAG.getConstant(NumSHLBits, dl, ShiftAmountTy);
7694 SDValue ShiftedLoad =
7733 SDValue PtrOff =
7736 SDValue Store =
7749 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
7751 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Add, MachinePointerInfo());
7775 SDValue PtrOff =
7794 SDValue ArgAsInt =
7812 SDValue MSWAsI64 = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgAsInt,
7845 SDValue Val = DAG.getCopyFromReg(Chain, dl, TOCBaseReg, PtrVT);
7846 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
7847 SDValue StackPtr = DAG.getRegister(StackPtrReg, PtrVT);
7848 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
7856 SDValue InGlue;
7881 SDValue
7882 PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
7885 const SmallVectorImpl<SDValue> &OutVals,
7895 SDValue Glue;
7896 SmallVector<SDValue, 4> RetOps(1, Chain);
7903 SDValue Arg = OutVals[RealResIdx];
7921 SDValue SVal =
7946 SDValue
7947 PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op,
7955 SDValue Chain = Op.getOperand(0);
7956 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
7958 SDValue Ops[2] = {Chain, FPSIdx};
7963 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op,
7974 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
7977 SDValue Chain = Op.getOperand(0);
7978 SDValue SaveSP = Op.getOperand(1);
7981 SDValue LoadLinkSP =
7991 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
8013 SDValue
8036 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8040 SDValue Chain = Op.getOperand(0);
8041 SDValue Size = Op.getOperand(1);
8047 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
8050 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
8051 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
8058 SDValue PPCTargetLowering::LowerEH_DWARF_CFA(SDValue Op,
8069 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
8077 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
8084 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
8096 SDValue Chain = LD->getChain();
8097 SDValue BasePtr = LD->getBasePtr();
8100 SDValue NewLD =
8103 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
8105 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
8109 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
8121 SDValue Chain = ST->getChain();
8122 SDValue BasePtr = ST->getBasePtr();
8123 SDValue Value = ST->getValue();
8132 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8140 SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
8169 return SDValue();
8171 SDValue N1 = Op.getOperand(0);
8177 return SDValue();
8179 return SDValue();
8185 SDValue Op1, Op2;
8223 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
8227 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8228 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
8235 SDValue Z = DAG.getSetCC(
8238 SDValue Zero = DAG.getConstant(0, dl, Z.getValueType());
8275 SDValue Sel1;
8311 SDValue Cmp;
8377 static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
8389 SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
8390 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
8420 SDValue Conv;
8431 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
8434 SDValue Tmp = convertFPToInt(Op, DAG, Subtarget);
8442 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
8448 SDValue Chain = IsStrict ? Tmp.getValue(1) : DAG.getEntryNode();
8455 SDValue Ops[] = { Chain, Tmp, FIPtr };
8478 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
8481 SDValue Conv = convertFPToInt(Op, DAG, Subtarget);
8482 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
8489 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
8494 SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
8500 return Subtarget.hasP9Vector() ? Op : SDValue();
8513 SDValue Lo, Hi;
8519 SDValue Res = DAG.getNode(PPCISD::STRICT_FADDRTZ, dl,
8526 SDValue Res = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8532 SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT);
8533 SDValue SignMask = DAG.getConstant(0x80000000, dl, DstVT);
8539 SDValue Chain = Op.getOperand(0);
8544 SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT,
8548 SDValue FltOfs = DAG.getSelect(
8552 SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl,
8556 SDValue SInt = DAG.getNode(ISD::STRICT_FP_TO_SINT, dl,
8560 SDValue IntOfs = DAG.getSelect(
8562 SDValue Result = DAG.getNode(ISD::XOR, dl, DstVT, SInt, IntOfs);
8567 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, Src, Cst);
8570 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src);
8576 return SDValue();
8597 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
8647 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
8654 bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
8683 static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG,
8685 SDValue Chain = SDValue()) {
8712 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
8720 SDValue Src = Op.getOperand(Op->isStrictFPOpcode() ? 1 : 0);
8725 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src);
8729 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) {
8740 SmallVector<SDValue, 16> Ops(NumConcat);
8742 SDValue UndefVec = DAG.getUNDEF(VecVT);
8749 SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
8753 SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
8767 SDValue Wide = widenVec(DAG, Src, dl);
8785 SDValue ShuffleSrc2 =
8787 SDValue Arrange = DAG.getVectorShuffle(WideVT, dl, Wide, ShuffleSrc2, ShuffV);
8789 SDValue Extend;
8809 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
8815 SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
8816 SDValue Chain = IsStrict ? Op.getOperand(0) : DAG.getEntryNode();
8830 return Subtarget.hasP9Vector() ? Op : SDValue();
8834 return SDValue();
8837 SDValue Sel = DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Src,
8856 SDValue SINT = Src;
8877 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
8893 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
8906 SDValue Bits;
8919 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8930 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8945 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
8947 SDValue Store = DAG.getStore(Chain, dl, SINT.getOperand(0), FIdx,
8964 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8973 SDValue FP = convertIntToFP(Op, Bits, DAG, Subtarget, Chain);
9000 SDValue Ld;
9006 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
9008 SDValue Store = DAG.getStore(Chain, dl, Src, FIdx,
9026 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
9039 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
9041 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, Src);
9044 SDValue Store = DAG.getStore(
9057 SDValue FP = convertIntToFP(Op, Ld, DAG, Subtarget, Chain);
9072 SDValue PPCTargetLowering::LowerSET_ROUNDING(SDValue Op,
9077 SDValue Chain = Op.getOperand(0);
9085 return SDValue(
9095 {DAG.getConstant(31, Dl, MVT::i32, true), SDValue(SetHi, 0)});
9096 return SDValue(SetLo, 0);
9100 SDValue One = DAG.getConstant(1, Dl, MVT::i32);
9101 SDValue SrcFlag = DAG.getNode(ISD::AND, Dl, MVT::i32, Op.getOperand(1),
9103 SDValue DstFlag = DAG.getNode(
9111 SDValue MFFS;
9116 SDValue NewFPSCR;
9128 NewFPSCR = SDValue(InsertRN, 0);
9134 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
9135 SDValue Addr = Subtarget.isLittleEndian()
9143 SDValue Tmp =
9146 Tmp = SDValue(DAG.getMachineNode(
9159 return SDValue(DAG.getMachineNode(PPC::MFFSCRN, Dl, {MVT::f64, MVT::Other},
9162 SDValue Zero = DAG.getConstant(0, Dl, MVT::i32, true);
9166 return SDValue(MTFSF, 0);
9169 SDValue PPCTargetLowering::LowerGET_ROUNDING(SDValue Op,
9196 SDValue Chain = Op.getOperand(0);
9197 SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain);
9200 SDValue CWD;
9207 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
9213 SDValue Four = DAG.getConstant(4, dl, PtrVT);
9214 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
9220 SDValue CWD1 =
9223 SDValue CWD2 =
9231 SDValue RetVal =
9241 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
9251 SDValue Lo = Op.getOperand(0);
9252 SDValue Hi = Op.getOperand(1);
9253 SDValue Amt = Op.getOperand(2);
9256 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
9258 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
9259 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
9260 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
9261 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9263 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
9264 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
9265 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
9266 SDValue OutOps[] = { OutLo, OutHi };
9270 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
9280 SDValue Lo = Op.getOperand(0);
9281 SDValue Hi = Op.getOperand(1);
9282 SDValue Amt = Op.getOperand(2);
9285 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
9287 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
9288 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
9289 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
9290 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9292 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
9293 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
9294 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
9295 SDValue OutOps[] = { OutLo, OutHi };
9299 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
9308 SDValue Lo = Op.getOperand(0);
9309 SDValue Hi = Op.getOperand(1);
9310 SDValue Amt = Op.getOperand(2);
9313 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
9315 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
9316 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
9317 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
9318 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9320 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
9321 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
9322 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
9324 SDValue OutOps[] = { OutLo, OutHi };
9328 SDValue PPCTargetLowering::LowerFunnelShift(SDValue Op,
9335 SDValue X = Op.getOperand(0);
9336 SDValue Y = Op.getOperand(1);
9337 SDValue Z = Op.getOperand(2);
9346 SDValue SubZ =
9359 static SDValue getCanonicalConstSplat(uint64_t Val, unsigned SplatSize, EVT VT,
9385 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG,
9394 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
9404 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
9405 SDValue Op2, SelectionDAG &DAG, const SDLoc &dl,
9414 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT,
9423 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
9451 SDValue Op0 = V->getOperand(0);
9481 SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
9484 SDValue Op0 = Op->getOperand(0);
9488 return SDValue();
9490 SDValue Lo = Op0.getOperand(0);
9491 SDValue Hi = Op0.getOperand(1);
9493 return SDValue();
9501 static const SDValue *getNormalLoadInput(const SDValue &Op, bool &IsPermuted) {
9502 const SDValue *InputLoad = &Op;
9556 static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op,
9597 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
9621 SDValue SplatNode = DAG.getNode(
9630 SDValue SplatNode = DAG.getUNDEF(MVT::v2i64);
9659 const SDValue *InputLoad = &Op.getOperand(0);
9678 for (SDValue BVInOp : Op->ops())
9698 return SDValue();
9707 return SDValue();
9712 SDValue Ops[] = {
9717 SDValue LdSplt = DAG.getMemIntrinsicNode(
9735 return SDValue();
9748 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32);
9791 SDValue Elt = DAG.getSignedConstant(SextVal, dl, MVT::i32);
9794 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
9795 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
9807 SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl);
9810 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
9835 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl);
9846 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl);
9858 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl);
9869 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl);
9875 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl);
9881 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl);
9887 return SDValue();
9892 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
9893 SDValue RHS, SelectionDAG &DAG,
9918 SDValue OpLHS, OpRHS;
9963 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
9967 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be handled
9969 /// SDValue.
9970 SDValue PPCTargetLowering::lowerToVINSERTB(ShuffleVectorSDNode *N,
9975 SDValue V1 = N->getOperand(0);
9976 SDValue V2 = N->getOperand(1);
10050 return SDValue();
10059 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2,
10068 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be handled
10070 /// SDValue.
10071 SDValue PPCTargetLowering::lowerToVINSERTH(ShuffleVectorSDNode *N,
10077 return SDValue();
10081 SDValue V1 = N->getOperand(0);
10082 SDValue V2 = N->getOperand(1);
10156 return SDValue();
10164 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10167 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2,
10169 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl);
10170 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
10174 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10175 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2,
10180 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
10182 /// return the default SDValue.
10183 SDValue PPCTargetLowering::lowerToXXSPLTI32DX(ShuffleVectorSDNode *SVN,
10187 SDValue LHS = peekThroughBitcasts(SVN->getOperand(0));
10188 SDValue RHS = peekThroughBitcasts(SVN->getOperand(1));
10191 SDValue VecShuffle(SVN, 0);
10196 return SDValue();
10204 return SDValue();
10211 return SDValue();
10220 return SDValue();
10229 SDValue Index;
10240 return SDValue();
10248 SDValue SplatNode = DAG.getNode(
10258 SDValue PPCTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
10263 SDValue N0 = peekThroughBitcasts(Op.getOperand(0));
10264 SDValue N1 = peekThroughBitcasts(Op.getOperand(1));
10270 if (SDValue Shuffle =
10275 SDValue ArgVal = DAG.getBitcast(MVT::i128, N0);
10276 SDValue SHLOp = DAG.getNode(ISD::SHL, dl, MVT::i128, ArgVal,
10278 SDValue SRLOp = DAG.getNode(ISD::SRL, dl, MVT::i128, ArgVal,
10280 SDValue OROp = DAG.getNode(ISD::OR, dl, MVT::i128, SHLOp, SRLOp);
10288 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
10291 SDValue V1 = Op.getOperand(0);
10292 SDValue V2 = Op.getOperand(1);
10298 if (SDValue NewShuffle = combineVectorShuffle(SVOp, DAG)) {
10316 const SDValue *InputLoad = getNormalLoadInput(V1, IsPermutedLoad);
10349 SDValue BasePtr = LD->getBasePtr();
10353 SDValue Ops[] = {
10360 SDValue LdSplt =
10381 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10382 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2);
10384 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2,
10386 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl,
10390 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2,
10396 SDValue SplatInsertNode;
10402 SDValue NewISDNode;
10414 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10415 SDValue Conv2 =
10418 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2,
10427 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1);
10428 SDValue Conv2 =
10431 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2,
10438 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10439 SDValue ReveHWord = DAG.getNode(ISD::BSWAP, dl, MVT::v8i16, Conv);
10442 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10443 SDValue ReveWord = DAG.getNode(ISD::BSWAP, dl, MVT::v4i32, Conv);
10446 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1);
10447 SDValue ReveDWord = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Conv);
10450 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1);
10451 SDValue ReveQWord = DAG.getNode(ISD::BSWAP, dl, MVT::v1i128, Conv);
10460 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
10461 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
10468 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10469 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv);
10583 SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
10585 SDValue V1, SDValue V2) const {
10638 SmallVector<SDValue, 16> ResultMask;
10686 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
10707 SDValue VPERMNode =
10717 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
11002 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
11017 SDValue Src = Op.getOperand(1);
11035 return SDValue(
11053 return SDValue(DAG.getMachineNode(
11067 return SDValue(
11078 SDValue WideVec =
11079 SDValue(DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes,
11082 SmallVector<SDValue, 4> RetOps;
11083 SDValue Value = SDValue(WideVec.getNode(), 0);
11084 SDValue Value2 = SDValue(WideVec.getNode(), 1);
11086 SDValue Extract;
11117 SDValue WideVec = Op.getOperand(1);
11122 SmallVector<SDValue, 4> RetOps;
11124 SDValue Extract = DAG.getNode(
11138 return SDValue();
11143 SDValue WideVec = Op.getOperand(1);
11145 return SDValue();
11176 return SDValue(
11179 {SDValue(DAG.getMachineNode(PPC::XSCMPEXPDP, dl, MVT::i32,
11191 return SDValue(
11194 {SDValue(DAG.getMachineNode(CmprOpc, dl, MVT::i32, Op.getOperand(2),
11217 std::pair<SDValue, SDValue> Result =
11219 dl, SDValue());
11240 SDValue Res = Op.getOperand(I);
11254 return SDValue(); // Don't custom lower most intrinsics.
11258 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
11265 SDValue Ops[] = {
11271 SDValue CompNode = DAG.getNode(PPCISD::VCMP_rec, dl, VTs, Ops);
11306 SDValue GlueOp = CompNode.getValue(1);
11308 SDValue SubRegIdx = DAG.getTargetConstant(Bitx, dl, MVT::i32);
11309 SDValue CR6Reg = DAG.getRegister(PPC::CR6, MVT::i32);
11310 SDValue CRBit =
11311 SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::i1,
11319 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
11336 SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
11345 SDValue Val = Op.getOperand(ArgStart + 1);
11353 return SDValue(
11363 return SDValue();
11367 SDValue PPCTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
11387 SDValue PPCTargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op,
11397 SDValue CmpOp = Op.getOperand(2);
11405 SDValue NewCmpOp =
11410 SmallVector<SDValue, 4> Ops;
11421 SDValue PPCTargetLowering::LowerATOMIC_LOAD_STORE(SDValue Op,
11434 SmallVector<SDValue, 4> Ops{
11439 SDValue LoadedVal = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, Tys,
11441 SDValue ValLo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal);
11442 SDValue ValHi =
11446 SDValue Val =
11455 SmallVector<SDValue, 4> Ops{
11458 SDValue Val = N->getOperand(1);
11459 SDValue ValLo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i64, Val);
11460 SDValue ValHi = DAG.getNode(ISD::SRL, dl, MVT::i128, Val,
11474 static SDValue getDataClassTest(SDValue Op, FPClassTest Mask, const SDLoc &Dl,
11502 SDValue Rev = getDataClassTest(Op, ~Mask, Dl, DAG, Subtarget);
11509 SDValue Rev(DAG.getMachineNode(
11518 SDValue Sign(
11522 SDValue Normal(DAG.getNOT(
11524 SDValue(DAG.getMachineNode(
11531 SDValue Result = DAG.getNode(ISD::AND, Dl, MVT::i1, Sign, Normal);
11544 SDValue NanCheck = getDataClassTest(Op, fcNan, Dl, DAG, Subtarget);
11548 SDValue HighWord;
11560 SDValue Vec = DAG.getBitcast(
11571 SDValue NanRes = DAG.getSetCC(
11600 return SDValue(
11603 SDValue(DAG.getMachineNode(
11611 SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
11614 SDValue LHS = Op.getOperand(0);
11627 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
11632 SDValue Op0 = Op.getOperand(0);
11651 SDValue Ops[] = {RLI.Chain, RLI.Ptr, DAG.getValueType(Op.getValueType())};
11652 SDValue Bits = DAG.getMemIntrinsicNode(
11664 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
11666 SDValue Val = Op0;
11677 SDValue ShiftBy = DAG.getConstant(
11680 SDValue Plus8 =
11682 SDValue Store2 =
11684 SDValue Store = DAG.getStore(Store2, dl, Val, FIdx, MachinePointerInfo());
11690 SDValue Store =
11696 SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11705 SDValue V1 = Op.getOperand(0);
11706 SDValue V2 = Op.getOperand(1);
11722 SDValue BitcastVector = DAG.getBitcast(MVT::v4i32, V1);
11723 SDValue BitcastLoad = DAG.getBitcast(MVT::i32, V2);
11724 SDValue InsVecElt =
11733 return SDValue();
11744 return SDValue();
11748 SDValue Mtvsrz = DAG.getNode(PPCISD::MTVSRZ, dl, VT, V2);
11761 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
11765 SDValue LoadChain = LN->getChain();
11766 SDValue BasePtr = LN->getBasePtr();
11780 SmallVector<SDValue, 4> Loads;
11781 SmallVector<SDValue, 4> LoadChains;
11784 SDValue Load =
11798 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
11799 SDValue Value =
11802 SDValue RetOps[] = {Value, TF};
11806 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
11810 SDValue StoreChain = SN->getChain();
11811 SDValue BasePtr = SN->getBasePtr();
11812 SDValue Value = SN->getValue();
11813 SDValue Value2 = SN->getValue();
11827 SmallVector<SDValue, 4> Stores;
11835 Value = SDValue(ExtNode, 0);
11836 Value2 = SDValue(ExtNode, 1);
11843 SDValue Elt;
11853 SDValue Store =
11862 SDValue TF = DAG.getTokenFactor(dl, Stores);
11866 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
11869 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
11871 SDValue Zero = getCanonicalConstSplat(0, 1, MVT::v4i32, DAG, dl);
11873 SDValue Neg16 = getCanonicalConstSplat(-16, 4, MVT::v4i32, DAG, dl);
11874 SDValue RHSSwap = // = vrlw RHS, 16
11884 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
11887 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
11894 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
11898 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
11903 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
11930 SDValue PPCTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
11934 return SDValue();
11940 SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
11949 return SDValue();
11952 SDValue Op0 = Op.getOperand(0);
11956 return SDValue();
11963 return SDValue();
11968 return SDValue();
11984 SDValue NewLoad[2];
11987 SDValue LdOp = Op0.getOperand(i);
11989 return SDValue();
11992 SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr()};
11997 SDValue NewOp =
12005 SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr()};
12006 SDValue NewLd = DAG.getMemIntrinsicNode(
12016 SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
12021 return SDValue();
12026 return SDValue();
12030 SDValue LHS = Op.getOperand(0);
12031 SDValue RHS = Op.getOperand(1);
12036 return SDValue();
12040 SDValue ADDC;
12041 SDValue Overflow;
12048 SDValue OverflowTrunc =
12050 SDValue Res =
12055 SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
12058 SDValue LHS = Op.getOperand(0);
12059 SDValue RHS = Op.getOperand(1);
12062 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
12064 SDValue Xor1 = DAG.getNode(ISD::XOR, dl, VT, RHS, LHS);
12065 SDValue Xor2 = DAG.getNode(ISD::XOR, dl, VT, Sub, LHS);
12067 SDValue And = DAG.getNode(ISD::AND, dl, VT, Xor1, Xor2);
12069 SDValue Overflow =
12073 SDValue OverflowTrunc =
12081 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12159 case ISD::INTRINSIC_W_CHAIN: return SDValue();
12181 SmallVectorImpl<SDValue>&Results,
12188 SDValue Res = LowerATOMIC_LOAD_STORE(SDValue(N, 0), DAG);
12195 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
12211 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
12228 Results.push_back(LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), DAG));
12240 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG);
12255 SDValue LoweredValue = LowerFP_TO_INT(SDValue(N, 0), DAG, dl);
12264 SDValue Lowered = LowerTRUNCATEVector(SDValue(N, 0), DAG);
12270 SDValue Lowered = LowerSCALAR_TO_VECTOR(SDValue(N, 0), DAG);
12283 SDValue Lowered = LowerFP_EXTEND(SDValue(N, 0), DAG);
13996 SDValue PPCTargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
14007 SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op);
14019 SDValue SRIdxVal = DAG.getTargetConstant(PPC::sub_eq, DL, MVT::i32);
14020 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i1,
14025 SDValue
14026 PPCTargetLowering::getSqrtResultForDenormInput(SDValue Op,
14037 SDValue PPCTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
14054 return SDValue();
14057 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
14069 return SDValue();
14097 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
14109 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
14115 SDValue BaseLoc = Base->getBasePtr();
14128 SDValue Base1 = Loc, Base2 = BaseLoc;
14154 SDValue Loc = LS->getBasePtr();
14227 SDValue Chain = LD->getChain();
14292 static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement,
14324 SDValue PPCTargetLowering::ConvertSETCCToSubtract(SDNode *N,
14334 return SDValue();
14340 return SDValue();
14361 return SDValue();
14364 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
14381 return SDValue();
14385 return SDValue();
14399 return SDValue();
14406 : SDValue());
14421 return SDValue();
14437 return SDValue();
14449 return SDValue();
14451 SmallVector<SDValue, 4> Inputs;
14452 SmallVector<SDValue, 8> BinOps, PromOps;
14472 SDValue BinOp = BinOps.pop_back_val();
14505 return SDValue();
14519 return SDValue();
14528 return SDValue();
14532 return SDValue();
14540 return SDValue();
14549 return SDValue();
14553 return SDValue();
14578 SDValue PromOp = PromOpHandles.back().getValue();
14592 SDValue RepValue = PromOp.getOperand(0);
14619 SmallVector<SDValue, 3> Ops(PromOp.getNode()->ops());
14636 return SDValue(N, 0);
14639 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
14660 return SDValue();
14664 return SDValue();
14671 return SDValue();
14673 SmallVector<SDValue, 4> Inputs;
14674 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
14680 SDValue BinOp = BinOps.pop_back_val();
14706 return SDValue();
14724 return SDValue();
14746 return SDValue();
14800 SDValue InSrc = Inputs[i].getOperand(0);
14823 SDValue PromOp = PromOpHandles.back().getValue();
14858 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
14907 SDValue ShiftCst =
14915 SDValue PPCTargetLowering::combineSetCC(SDNode *N,
14922 SDValue LHS = N->getOperand(0);
14923 SDValue RHS = N->getOperand(1);
14938 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
14947 static bool isFPExtLoad(SDValue Op) {
14961 SDValue PPCTargetLowering::
14970 SDValue FirstInput = N->getOperand(0);
14985 SmallVector<SDValue, 4> Ops;
14988 SDValue NextOp = N->getOperand(i);
14990 return SDValue();
14993 return SDValue();
14999 return SDValue();
15008 return SDValue();
15012 SDValue In = N->getOperand(i).getOperand(0);
15019 SDValue Trunc =
15036 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
15039 return SDValue();
15048 static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) {
15056 return SDValue();
15061 SDValue FirstInput = N->getOperand(0);
15073 return SDValue();
15083 return SDValue();
15085 SDValue NextInput = IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) :
15088 return SDValue();
15090 SDValue PreviousInput =
15097 return SDValue();
15108 return SDValue();
15115 SDValue WideLoad;
15116 SDValue ReturnSDVal;
15136 return SDValue();
15146 static SDValue addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG,
15147 SDValue Input, uint64_t Elems,
15166 SDValue Shuffle =
15171 SDValue Conv = DAG.getBitcast(VT, Shuffle);
15185 static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) {
15206 SDValue Input;
15208 auto isSExtOfVecExtract = [&](SDValue Op) -> bool {
15217 SDValue Extract = Op.getOperand(0);
15245 return SDValue();
15265 return SDValue();
15276 return SDValue();
15283 static SDValue combineBVZEXTLOAD(SDNode *N, SelectionDAG &DAG) {
15288 return SDValue();
15290 SDValue Operand = N->getOperand(0);
15294 return SDValue();
15308 return SDValue();
15310 SDValue LoadOps[] = {
15319 SDValue PPCTargetLowering::DAGCombineBuildVector(SDNode *N,
15328 return SDValue();
15333 SDValue FirstInput = N->getOperand(0);
15335 SDValue Reduced = combineElementTruncationToVectorTruncation(N, DCI);
15342 SDValue Reduced = combineBVOfConsecutiveLoads(N, DAG);
15360 SDValue BVOfZLoad = combineBVZEXTLOAD(N, DAG);
15366 return SDValue();
15372 return SDValue();
15375 return SDValue();
15377 return SDValue();
15379 SDValue Ext1 = FirstInput.getOperand(0);
15380 SDValue Ext2 = N->getOperand(1).getOperand(0);
15383 return SDValue();
15388 return SDValue();
15391 return SDValue();
15401 return SDValue();
15403 SDValue SrcVec = Ext1.getOperand(0);
15410 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
15417 return SDValue();
15421 SDValue Op(N, 0);
15426 return SDValue();
15428 return SDValue();
15431 return SDValue();
15433 SDValue FirstOperand(Op.getOperand(0));
15443 SDValue WidthConst =
15447 SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst };
15448 SDValue Ld = DAG.getMemIntrinsicNode(PPCISD::LXSIZX, dl,
15455 SDValue ExtOps[] = { Ld, WidthConst };
15456 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps);
15468 return SDValue();
15489 SDValue Src = Op.getOperand(0).getOperand(0);
15495 return SDValue();
15502 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
15503 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
15514 return SDValue();
15519 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
15524 return SDValue();
15528 SDValue Chain;
15529 SDValue Base;
15544 return SDValue();
15560 SDValue LoadOps[] = { Chain, Base };
15561 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
15567 SDValue Swap = DAG.getNode(
15573 SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
15585 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
15590 return SDValue();
15594 SDValue Chain;
15595 SDValue Base;
15612 return SDValue();
15626 SDValue Src = N->getOperand(SrcOpnd);
15635 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
15639 SDValue StoreOps[] = { Chain, Swap, Base };
15640 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
15648 SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
15660 SDValue Val = N->getOperand(1).getOperand(Strict ? 1 : 0);
15665 return SDValue();
15674 return SDValue();
15678 return SDValue();
15684 SDValue Ops[] = {N->getOperand(0), Val, N->getOperand(2),
15710 static bool isSplatBV(SDValue Op) {
15713 SDValue FirstOp;
15729 static SDValue isScalarToVec(SDValue Op) {
15733 return SDValue();
15737 return SDValue();
15770 static SDValue getSToVPermuted(SDValue OrigSToV, SelectionDAG &DAG,
15776 SDValue Input = OrigSToV.getOperand(0);
15780 SDValue OrigVector = Input.getOperand(0);
15818 static SDValue generateSToVPermutedForVecShuffle(
15820 int FirstElt, int &LastElt, SDValue VecShuffOperand, SDValue SToVNode,
15839 SDValue SToVPermuted = getSToVPermuted(SToVNode, DAG, Subtarget);
15857 SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
15859 SDValue LHS = SVN->getOperand(0);
15860 SDValue RHS = SVN->getOperand(1);
15863 SDValue Res(SVN, 0);
15889 SDValue SToVLHS = isScalarToVec(LHS);
15890 SDValue SToVRHS = isScalarToVec(RHS);
15959 SDValue TheSplat = IsLittleEndian ? RHS : LHS;
16017 SDValue SplatVal =
16028 SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
16052 return SDValue();
16058 return SDValue();
16061 return SDValue();
16070 return SDValue();
16073 SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()};
16084 return SDValue();
16087 SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0),
16097 static bool isStoreConditional(SDValue Intrin, unsigned &StoreWidth) {
16112 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
16124 SDValue Op1 = N->getOperand(0);
16125 SDValue Op2 = N->getOperand(1);
16131 SDValue NarrowOp = Op1.getOperand(0);
16140 SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32);
16141 SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp);
16177 if (SDValue CSCC = combineSetCC(N, DCI))
16198 SDValue Val = combineStoreFPToInt(N, DCI);
16205 SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI);
16222 SDValue BSwapOp = N->getOperand(1).getOperand(0);
16238 SDValue Ops[] = {
16255 SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);
16263 return SDValue(N, 0);
16357 SDValue BasePtr = LD->getBasePtr();
16368 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr,
16371 SDValue AddPtr =
16374 SDValue FloatLoad2 = DAG.getLoad(
16375 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr,
16382 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), BasePtr);
16388 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, LD->isIndexed() ? 2 : 1),
16389 SDValue(FloatLoad2.getNode(), 1));
16394 return SDValue(N, 0);
16407 SDValue Chain = LD->getChain();
16408 SDValue Ptr = LD->getBasePtr();
16445 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
16459 SDValue LDXIntID =
16461 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
16462 SDValue BaseLoad =
16484 SDValue Increment =
16491 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
16492 SDValue ExtraLoad =
16497 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16505 SDValue Perm;
16524 return SDValue(N, 0);
16534 SDValue Add = N->getOperand(1);
16549 return SDValue(U, 0);
16566 return SDValue(V, 0);
16580 SDValue V1 = N->getOperand(1);
16581 SDValue V2 = N->getOperand(2);
16630 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), N->getOperand(0));
16632 return SDValue();
16667 SDValue Load = N->getOperand(0);
16670 SDValue Ops[] = {
16675 SDValue BSLoad =
16682 SDValue ResVal = BSLoad;
16695 return SDValue(N, 0);
16701 return SDValue();
16706 return SDValue();
16707 SDValue BasePtr = LD->getBasePtr();
16708 SDValue Lo = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr,
16715 SDValue Hi = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, NewMMO);
16717 SDValue Res;
16722 SDValue TF =
16725 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), TF);
16764 if (User->getOperand(i) == SDValue(VCMPrecNode, 1)) {
16774 return SDValue(VCMPrecNode, 0);
16785 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
16811 return SDValue();
16817 if (SDValue Impossible = isImpossibleCompare())
16829 SDValue Ops[] = {LHS.getOperand(0), LHS.getOperand(2), LHS.getOperand(3),
16832 SDValue ConstSt = DAG.getMemIntrinsicNode(
16837 SDValue InChain;
16842 SmallVector<SDValue, 4> InChains;
16843 SDValue InTF = N->getOperand(0);
16860 if (SDValue Impossible = isImpossibleCompare())
16865 SDValue Ops[] = {
16871 SDValue CompNode = DAG.getNode(PPCISD::VCMP_rec, dl, VTs, Ops);
16902 return SDValue();
16905 SDValue
16912 return SDValue();
16915 return SDValue();
16918 SDValue N0 = N->getOperand(0);
16922 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
16924 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
16939 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
17269 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17271 std::vector<SDValue> &Ops,
17273 SDValue Result;
17345 SmallVectorImpl<SDValue> &Ops,
17405 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
17412 return SDValue();
17427 SDValue FrameAddr =
17430 SDValue Offset =
17439 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
17444 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
17464 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
17501 bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
17744 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17820 SDValue C) const {
17981 SDValue PPCTargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
17986 return SDValue();
17998 SDValue N0 = Op.getOperand(0);
17999 SDValue N1 = Op.getOperand(1);
18000 SDValue N2 = Op.getOperand(2);
18004 SDValue NegN2 =
18008 return SDValue();
18017 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize,
18021 SDValue NegN1 = getNegatedExpression(N1, DAG, LegalOps, OptForSize,
18104 static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
18106 SDValue N0 = N->getOperand(0);
18107 SDValue N1 = N->getOperand(1);
18133 return SDValue();
18136 SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
18140 SDValue N0 = N->getOperand(0);
18146 return SDValue();
18150 SDValue ExtsSrc = N0.getOperand(0);
18153 return SDValue();
18156 SDValue ShiftBy = SDValue(CN1, 0);
18166 SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {
18170 return SDValue();
18173 SDValue PPCTargetLowering::combineSRL(SDNode *N, DAGCombinerInfo &DCI) const {
18177 return SDValue();
18184 static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
18187 return SDValue();
18189 SDValue LHS = N->getOperand(0);
18190 SDValue RHS = N->getOperand(1);
18192 auto isZextOfCompareWithConstant = [](SDValue Op) {
18197 SDValue Cmp = Op.getOperand(0);
18219 return SDValue();
18223 SDValue Cmp = RHS.getOperand(0);
18224 SDValue Z = Cmp.getOperand(0);
18237 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
18239 SDValue AddOrZ = NegConstant != 0 ? Add : Z;
18240 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
18243 SDValue(Addc.getNode(), 1));
18252 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
18254 SDValue AddOrZ = NegConstant != 0 ? Add : Z;
18255 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
18258 SDValue(Subc.getNode(), 1));
18262 return SDValue();
18270 static SDValue combineADDToMAT_PCREL_ADDR(SDNode *N, SelectionDAG &DAG,
18273 return SDValue();
18277 SDValue LHS = N->getOperand(0);
18278 SDValue RHS = N->getOperand(1);
18284 return SDValue();
18292 return SDValue();
18299 return SDValue();
18303 SDValue GA =
18306 SDValue MatPCRel =
18311 SDValue PPCTargetLowering::combineADD(SDNode *N, DAGCombinerInfo &DCI) const {
18318 return SDValue();
18330 SDValue PPCTargetLowering::combineTRUNCATE(SDNode *N,
18335 if (SDValue CRTruncValue = DAGCombineTruncBoolExt(N, DCI))
18340 SDValue Op0 = N->getOperand(0);
18344 return SDValue();
18353 return SDValue();
18365 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0));
18370 return SDValue();
18373 SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {
18378 return SDValue();
18383 return SDValue();
18425 return SDValue();
18427 SDValue Op0 = N->getOperand(0);
18428 SDValue Op1 =
18431 SDValue Res = DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
18442 return SDValue();
18444 SDValue Op0 = N->getOperand(0);
18445 SDValue Op1 =
18455 return SDValue();
18461 SDValue PPCTargetLowering::combineFMALike(SDNode *N,
18463 SDValue N0 = N->getOperand(0);
18464 SDValue N1 = N->getOperand(1);
18465 SDValue N2 = N->getOperand(2);
18476 return SDValue();
18481 return SDValue();
18485 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize))
18490 if (SDValue NegN1 = getCheaperNegatedExpression(N1, DAG, LegalOps, CodeSize))
18493 return SDValue();
18570 static void setAlignFlagsForFI(SDValue N, unsigned &FlagSet,
18599 static void computeFlagsForAddressComputation(SDValue N, unsigned &FlagSet,
18629 SDValue RHS = N.getOperand(1);
18651 static bool isPCRelNode(SDValue N) {
18661 unsigned PPCTargetLowering::computeMOFlags(const SDNode *Parent, SDValue N,
18688 SDValue IntrinOp = (ID == Intrinsic::ppc_vsx_lxvp)
18779 PPC::AddrMode PPCTargetLowering::SelectForceXFormMode(SDValue N, SDValue &Disp,
18780 SDValue &Base,
18814 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
18831 SDValue PPCTargetLowering::lowerToLibCall(const char *LibCallName, SDValue Op,
18837 SDValue Callee =
18842 for (const SDValue &N : Op->op_values()) {
18852 SDValue InChain = DAG.getEntryNode();
18853 SDValue TCChain = InChain;
18870 SDValue PPCTargetLowering::lowerLibCallBasedOnType(
18871 const char *LibCallFloatName, const char *LibCallDoubleName, SDValue Op,
18879 return SDValue();
18882 bool PPCTargetLowering::isLowringToMASSFiniteSafe(SDValue Op) const {
18888 bool PPCTargetLowering::isLowringToMASSSafe(SDValue Op) const {
18896 SDValue PPCTargetLowering::lowerLibCallBase(const char *LibCallDoubleName,
18900 SDValue Op,
18903 return SDValue();
18913 SDValue PPCTargetLowering::lowerPow(SDValue Op, SelectionDAG &DAG) const {
18918 SDValue PPCTargetLowering::lowerSin(SDValue Op, SelectionDAG &DAG) const {
18923 SDValue PPCTargetLowering::lowerCos(SDValue Op, SelectionDAG &DAG) const {
18928 SDValue PPCTargetLowering::lowerLog(SDValue Op, SelectionDAG &DAG) const {
18933 SDValue PPCTargetLowering::lowerLog10(SDValue Op, SelectionDAG &DAG) const {
18938 SDValue PPCTargetLowering::lowerExp(SDValue Op, SelectionDAG &DAG) const {
18945 static void setXFormForUnalignedFI(SDValue N, unsigned Flags,
18958 SDValue N, SDValue &Disp,
18959 SDValue &Base,
18991 SDValue Op0 = N.getOperand(0);
18992 SDValue Op1 = N.getOperand(1);
19040 Base = SDValue(DAG.getMachineNode(LIS, DL, CNType, Base), 0);