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Searched defs:RegIdx (Results 1 – 24 of 24) sorted by relevance

/llvm-project/llvm/include/llvm/CodeGen/
H A DDetectDeadLanes.h57 const VRegInfo &getVRegInfo(unsigned RegIdx) const { in getVRegInfo()
61 bool isDefinedByCopy(unsigned RegIdx) const { in isDefinedByCopy()
101 void PutInWorklist(unsigned RegIdx) { in PutInWorklist()
/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.cpp508 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute() argument
471 defValue(unsigned RegIdx,const VNInfo * ParentVNI,SlotIndex Idx,bool Original) defValue() argument
548 buildCopy(Register FromReg,Register ToReg,LaneBitmask LaneMask,MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,bool Late,unsigned RegIdx) buildCopy() argument
592 defFromParent(unsigned RegIdx,const VNInfo * ParentVNI,SlotIndex UseIdx,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) defFromParent() argument
809 unsigned RegIdx = 0; leaveIntvAtTop() local
884 unsigned RegIdx = AssignI.value(); removeBackCopies() local
1146 unsigned RegIdx; transferValues() local
1285 unsigned RegIdx = RegAssign.lookup(V->def); extendPHIKillRanges() local
1300 unsigned RegIdx = RegAssign.lookup(V->def); extendPHIKillRanges() local
1323 unsigned RegIdx; rewriteAssigned() member
1347 unsigned RegIdx = RegAssign.lookup(Idx); rewriteAssigned() local
1513 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); finish() local
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H A DDetectDeadLanes.cpp279 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
456 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo() local
467 unsigned RegIdx = Worklist.front(); in computeSubRegisterLaneBitInfo() local
509 unsigned RegIdx = Register::virtReg2Index(Reg); in modifySubRegisterOperandStatus() local
H A DSplitKit.h349 LiveIntervalCalc &getLICalc(unsigned RegIdx) { in getLICalc()
/llvm-project/bolt/lib/Passes/
H A DStokeInfo.cpp38 for (int RegIdx : RegV.set_bits()) { in getRegNameFromBitVec() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
H A DARMISelLowering.cpp4557 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); LowerFormalArguments() local
/llvm-project/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp132 if (RegIdx >= NumOpRegs) in PrintAsmOperand() local
H A DAVRISelLowering.cpp1282 unsigned RegIdx = RegLastIdx + TotalBytes; analyzeArguments() local
1365 int RegIdx = TotalBytes - 1; analyzeReturnValues() local
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/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp299 unsigned RegIdx = Imm & 0xff; DECODE_OPERAND_REG_8() local
310 unsigned RegIdx = Imm & 0x7f; DecodeVGPR_16_Lo128RegisterClass() local
324 unsigned RegIdx = Imm & 0x7f; decodeOperand_VSrcT16_Lo128() local
340 unsigned RegIdx = Imm & 0xff; decodeOperand_VSrcT16() local
844 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; convertTrue16OpSel() local
1223 createVGPR16Operand(unsigned RegIdx,bool IsHi) const createVGPR16Operand() argument
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp547 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp841 SDValue RegIdx = Node->getOperand(2); trySelect() local
910 SDValue RegIdx = Node->getOperand(2); trySelect() local
/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp652 unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK; getMachineOpValueT16Lo128() local
/llvm-project/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp764 for (int64_t OpndIdx = 7, RegIdx = 0; expandVastartSaveXmmRegs() local
H A DX86SpeculativeLoadHardening.cpp1867 unsigned RegIdx = Log2_32(RegBytes); canHardenRegister() local
H A DX86FastISel.cpp2629 unsigned RegIdx = X86::sub_16bit; fastLowerIntrinsicCall() local
H A DX86InstrInfo.cpp5796 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); foldImmediateImpl() local
H A DX86ISelLowering.cpp36493 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { EmitSjLjDispatchBlock() local
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/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DVarLocBasedImpl.cpp1456 LocIndex RegIdx = LocIndex::fromRawInteger(*It); collectAllVarLocs() local
/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2819 unsigned RegIdx = RegNum / AlignSize; getRegularReg() local
4888 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); validateGWS() local
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3687 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); CC_LoongArch() local
/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp891 struct RegIdxOp RegIdx; global() member
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2284 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); allocateVGPR32Input() local
2306 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); allocateSGPR32InputImpl() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp19013 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); CC_RISCV() local