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Searched defs:DstReg (Results 1 – 25 of 128) sorted by relevance

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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp135 Register DstReg = Dst.getReg(); runOnMachineFunction() local
155 Register DstReg = Dst.getReg(); runOnMachineFunction() local
172 Register DstReg = Dst.getReg(); runOnMachineFunction() local
183 Register DstReg = Dst.getReg(); runOnMachineFunction() local
205 Register DstReg = Dst.getReg(); runOnMachineFunction() local
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/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp61 Register DstReg) { in buildMI()
154 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
187 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
247 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
307 Register DstReg = MI.getOperand(0).getReg(); in expand() local
361 Register DstReg = MI.getOperand(0).getReg(); in expand() local
426 Register DstReg = MI.getOperand(0).getReg(); in expand() local
458 Register DstReg = MI.getOperand(0).getReg(); in expand() local
497 Register DstReg = MI.getOperand(0).getReg(); in expand() local
530 Register DstReg = MI.getOperand(0).getReg(); in expand() local
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H A DAVRRegisterInfo.cpp113 foldFrameOffset(MachineBasicBlock::iterator & II,int & Offset,Register DstReg) foldFrameOffset() argument
169 Register DstReg = MI.getOperand(0).getReg(); eliminateFrameIndex() local
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp129 Register DstReg = MI.getOperand(0).getReg(); expandMOVImm() local
160 Register DstReg = MI.getOperand(0).getReg(); expandMOVImm() local
173 Register DstReg = MI.getOperand(0).getReg(); expandMOVImm() local
192 Register DstReg = MI.getOperand(0).getReg(); expandMOVImm() local
217 Register DstReg = MI.getOperand(0).getReg(); expandMOVImm() local
497 Register DstReg = MI.getOperand(0).getReg(); expand_DestructiveOp() local
1171 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
1297 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
1332 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
1374 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
1395 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
1440 Register DstReg = MI.getOperand(0).getReg(); expandMI() local
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H A DAArch64RedundantCopyElimination.cpp185 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
251 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); selectSHXADDOp() local
290 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); selectSHXADDOp() local
329 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); selectSHXADDOp() local
368 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); selectSHXADD_UWOp() local
564 Register DstReg = MI.getOperand(0).getReg(); select() local
576 Register DstReg = MI.getOperand(0).getReg(); select() local
774 Register DstReg = MI.getOperand(0).getReg(); preISelLower() local
783 Register DstReg = MI.getOperand(0).getReg(); preISelLower() local
891 Register DstReg = MI.getOperand(0).getReg(); selectCopy() local
918 const Register DstReg = MI.getOperand(0).getReg(); selectImplicitDef() local
933 materializeImm(Register DstReg,int64_t Imm,MachineIRBuilder & MIB) const materializeImm() argument
1129 Register DstReg = SelectMI.getReg(0); selectSelect() local
1207 Register DstReg = CmpMI.getReg(0); selectFPCompare() local
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/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp270 Register DstReg = I.getOperand(0).getReg(); selectCopy() local
758 selectTurnIntoCOPY(MachineInstr & I,MachineRegisterInfo & MRI,const unsigned DstReg,const TargetRegisterClass * DstRC,const unsigned SrcReg,const TargetRegisterClass * SrcRC) const selectTurnIntoCOPY() argument
779 const Register DstReg = I.getOperand(0).getReg(); selectTruncOrPtrToInt() local
843 const Register DstReg = I.getOperand(0).getReg(); selectZext() local
908 const Register DstReg = I.getOperand(0).getReg(); selectAnyext() local
1109 const Register DstReg = I.getOperand(0).getReg(); selectUAddSub() local
1212 const Register DstReg = I.getOperand(0).getReg(); selectExtract() local
1263 emitExtractSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitExtractSubreg() argument
1301 emitInsertSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitInsertSubreg() argument
1344 const Register DstReg = I.getOperand(0).getReg(); selectInsert() local
1429 Register DstReg = I.getOperand(0).getReg(); selectMergeValues() local
1503 const Register DstReg = I.getOperand(0).getReg(); materializeFP() local
1565 Register DstReg = I.getOperand(0).getReg(); selectImplicitDefOrPHI() local
1599 const Register DstReg = I.getOperand(0).getReg(); selectMulDivRem() local
1815 unsigned DstReg = Sel.getReg(0); selectSelect() local
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/llvm-project/llvm/lib/CodeGen/
H A DOptimizePHIs.cpp100 Register DstReg = MI->getOperand(0).getReg(); IsSingleValuePHICycle() local
144 Register DstReg = MI->getOperand(0).getReg(); IsDeadPHICycle() local
H A DTwoAddressInstructionPass.cpp290 isCopyToReg(MachineInstr & MI,Register & SrcReg,Register & DstReg,bool & IsSrcPhys,bool & IsDstPhys) const isCopyToReg() argument
387 Register SrcReg, DstReg; isKilled() local
398 isTwoAddrUse(MachineInstr & MI,Register Reg,Register & DstReg) isTwoAddrUse() argument
415 findOnlyInterestingUse(Register Reg,MachineBasicBlock * MBB,bool & IsCopy,Register & DstReg,bool & IsDstPhys) const findOnlyInterestingUse() argument
755 scanUses(Register DstReg) scanUses() argument
813 Register SrcReg, DstReg; processCopy() local
873 Register DstReg; rescheduleMIBelowKill() local
1056 Register DstReg; rescheduleKillAboveMI() local
1456 Register DstReg = DstMO.getReg(); collectTiedOperands() local
1837 Register DstReg = mi->getOperand(DstIdx).getReg(); runOnMachineFunction() local
1934 Register DstReg = MI.getOperand(0).getReg(); eliminateRegSequence() local
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H A DExpandPostRAPseudos.cpp66 Register DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local
H A DRegisterCoalescer.h33 Register DstReg; variable
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/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp133 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
191 const Register DstReg = I.getOperand(0).getReg(); in selectIntToFP() local
218 const Register DstReg = I.getOperand(0).getReg(); in selectFPToInt() local
243 const Register DstReg = I.getOperand(0).getReg(); in selectZExt() local
604 Register DstReg = I.getOperand(0).getReg(); in selectI64Imm() local
662 const Register DstReg = I.getOperand(0).getReg(); in selectConstantPool() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVPostRAExpandPseudoInsts.cpp92 Register DstReg = MBBI->getOperand(0).getReg(); expandMovImm() local
107 Register DstReg = MBBI->getOperand(0).getReg(); expandMovAddr() local
/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp192 Register &DstReg, const GlobalValue *GVal, bool IsAma) { in processCandidate()
226 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg()
330 Register DstReg = MI.getOperand(0).getReg(); in removeLD() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp192 Register DstReg = Copy.getOperand(0).getReg(); getCopyRegClasses() local
228 Register DstReg = MI.getOperand(0).getReg(); tryChangeVGPRtoSGPRinCopy() local
270 Register DstReg = MI.getOperand(0).getReg(); foldVGPRCopyIntoRegSequence() local
843 tryMoveVGPRConstToSGPR(MachineOperand & MaybeVGPRConstMO,Register DstReg,MachineBasicBlock * BlockToInsertTo,MachineBasicBlock::iterator PointToInsertTo) tryMoveVGPRConstToSGPR() argument
870 Register DstReg = MI.getOperand(0).getReg(); lowerSpecialCase() local
913 Register DstReg = MI->getOperand(0).getReg(); analyzeVGPRToSGPRCopy() local
1061 Register DstReg = MI->getOperand(0).getReg(); lowerVGPR2SGPRCopies() local
1108 Register DstReg = MI.getOperand(0).getReg(); fixSCCCopies() local
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H A DR600ExpandSpecialInstrs.cpp126 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
196 Register DstReg = in runOnMachineFunction() local
H A DSILowerI1Copies.cpp477 Register DstReg = MI.getOperand(0).getReg(); lowerCopiesFromI1() local
562 Register DstReg = MI->getOperand(0).getReg(); lowerPhis() local
669 Register DstReg = MI.getOperand(0).getReg(); lowerCopiesToI1() local
856 buildMergeLaneMasks(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,Register PrevReg,Register CurReg) buildMergeLaneMasks() argument
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H A DAMDGPURegisterBankInfo.cpp129 Register DstReg = MI.getOperand(0).getReg(); in applyBank() local
157 Register DstReg = MI.getOperand(0).getReg(); in applyBank() local
1059 Register DstReg = MI.getOperand(0).getReg(); in applyMappingLoad() local
1457 Register DstReg = MI.getOperand(0).getReg(); applyMappingBFE() local
1842 buildVCopy(MachineIRBuilder & B,Register DstReg,Register SrcReg) const buildVCopy() argument
1993 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; foldExtractEltToCmpSelect() local
2129 Register DstReg = MI.getOperand(0).getReg(); applyMappingSMULU64() local
2186 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2216 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2274 Register DstReg = MI.getOperand(BoolDstOp).getReg(); applyMappingImpl() local
2309 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2387 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2474 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2556 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2642 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2705 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2722 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2796 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
2925 Register DstReg = MI.getOperand(0).getReg(); applyMappingImpl() local
3793 Register DstReg = PHI->getReg(0); getInstrMapping() local
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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
126 Register DstReg = MI.getOperand(0).getReg(); tryCombineZExt() local
201 Register DstReg = MI.getOperand(0).getReg(); tryCombineSExt() local
266 Register DstReg = MI.getOperand(0).getReg(); tryCombineTrunc() local
387 Register DstReg = MI.getOperand(0).getReg(); tryFoldImplicitDef() local
565 replaceRegOrBuildCopy(Register DstReg,Register SrcReg,MachineRegisterInfo & MRI,MachineIRBuilder & Builder,SmallVectorImpl<Register> & UpdatedDefs,GISelChangeObserver & Observer) replaceRegOrBuildCopy() argument
1242 Register DstReg = MI.getOperand(Idx).getReg(); tryCombineUnmergeValues() local
1275 Register DstReg = MI.getOperand(0).getReg(); tryCombineExtract() local
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/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
536 unsigned DstReg, SrcReg; subInstWouldBeExtended() local
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/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp41 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,MCRegister DstReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
148 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DstReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
185 movImm(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,Register DstReg,uint64_t Val,MachineInstr::MIFlag Flag) const movImm() argument
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/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp79 Register DstReg = MI->getOperand(0).getReg(); visitMBB() local
/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp716 Register DstReg = I->getOperand(0).getReg(); in expandPseudoMTLoHi() local
733 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
755 Register DstReg in expandExtractElementF64() local
797 Register DstReg = I->getOperand(0).getReg(); expandBuildPairF64() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp52 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); in matchFConstantToConstant() local
243 Register DstReg = MI.getOperand(0).getReg(); matchExtAddvToUdotAddv() local
455 Register DstReg = MI.getOperand(0).getReg(); applyExtUaddvToUaddlv() local
562 matchPushAddSubExt(MachineInstr & MI,MachineRegisterInfo & MRI,Register DstReg,Register SrcReg1,Register SrcReg2) matchPushAddSubExt() argument
587 applyPushAddSubExt(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,bool isSExt,Register DstReg,Register SrcReg1,Register SrcReg2) applyPushAddSubExt() argument
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/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp84 Register DstReg = MBBI->getOperand(0).getReg(); in emitPrologue() local
170 Register DstReg = I->getOperand(1).getReg(); in emitEpilogue() local

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