Lines Matching defs:DstReg

204   Register DstReg = Copy.getOperand(0).getReg();
214   const TargetRegisterClass *DstRC = DstReg.isVirtual()
215                                          ? MRI.getRegClass(DstReg)
216                                          : TRI.getPhysRegBaseClass(DstReg);
240   Register DstReg = MI.getOperand(0).getReg();
242   if (!SrcReg.isVirtual() || !DstReg.isVirtual())
245   for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
259   MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
282   Register DstReg = MI.getOperand(0).getReg();
283   if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
286   if (!MRI.hasOneUse(DstReg))
289   MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
311   MRI.setRegClass(DstReg, DstRC);
853     MachineOperand &MaybeVGPRConstMO, Register DstReg,
870           TII->get(MoveOp), DstReg)
874   MaybeVGPRConstMO.setReg(DstReg);
880   Register DstReg = MI.getOperand(0).getReg();
882   if (!DstReg.isVirtual()) {
887     if (DstReg == AMDGPU::M0 &&
895     } else if (tryMoveVGPRConstToSGPR(MI.getOperand(1), DstReg, MI.getParent(),
923   Register DstReg = MI->getOperand(0).getReg();
924   const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1071     Register DstReg = MI->getOperand(0).getReg();
1080                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);
1084                          TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg);
1088                             TII->get(AMDGPU::REG_SEQUENCE), DstReg);
1116       Register DstReg = MI.getOperand(0).getReg();
1128                     TII->get(AMDGPU::COPY), DstReg)
1133       if (DstReg == AMDGPU::SCC) {