Lines Matching defs:DstReg

131   Register DstReg = MI.getOperand(0).getReg();
136   if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
162         Register DstReg = MI.getOperand(0).getReg();
166                 .addReg(DstReg, RegState::Define |
169                 .addReg(DstReg)
175       Register DstReg = MI.getOperand(0).getReg();
179               .addReg(DstReg, RegState::Define |
182               .addReg(DstReg)
183               .addReg(DstReg)
194         Register DstReg = MI.getOperand(0).getReg();
198                 .addReg(DstReg, RegState::Define |
201                 .addReg(DstReg)
211         .addReg(DstReg, RegState::Define |
219       Register DstReg = MI.getOperand(0).getReg();
222         .addReg(DstReg,
226         .addReg(DstReg)
499   Register DstReg = MI.getOperand(0).getReg();
507     if (DstReg == MI.getOperand(3).getReg()) {
523     if (DstReg == MI.getOperand(3).getReg()) {
527     } else if (DstReg == MI.getOperand(4).getReg()) {
543     DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg();
548       DstReg != MI.getOperand(DOPIdx).getReg() ||
557         DstReg != MI.getOperand(DOPIdx).getReg() ||
619                .addReg(DstReg, RegState::Define)
626     // Create the additional LSL to zero the lanes when the DstReg is not
634           .addReg(DstReg, RegState::Define)
636           .addReg(DstReg)
639   } else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
642                .addReg(DstReg, RegState::Define)
651     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
1199     Register DstReg = MI.getOperand(0).getReg();
1200     if (DstReg == MI.getOperand(3).getReg()) {
1209     } else if (DstReg == MI.getOperand(2).getReg()) {
1220       if (DstReg == MI.getOperand(1).getReg()) {
1232             .addReg(DstReg,
1241             .addReg(DstReg,
1325     Register DstReg = MI.getOperand(0).getReg();
1332                                         TII->get(AArch64::LDRXl), DstReg);
1348           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
1353         unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32);
1357                    .addReg(DstReg, RegState::Kill)
1358                    .addReg(DstReg, DstFlags | RegState::Implicit);
1360         Register DstReg = MI.getOperand(0).getReg();
1363                    .addUse(DstReg, RegState::Kill);
1402       Register DstReg = MI.getOperand(0).getReg();
1404           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1407                           TII->get(AArch64::LDRXui), DstReg)
1408                       .addUse(DstReg)
1423     Register DstReg = MI.getOperand(0).getReg();
1424     assert(DstReg != AArch64::XZR);
1426         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1440       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
1441           .addReg(DstReg)
1449             .addReg(DstReg)
1468     Register DstReg = MI.getOperand(0).getReg();
1479     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)