Lines Matching defs:DstReg

110                           const unsigned DstReg,
123   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
126   bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
278   Register DstReg = I.getOperand(0).getReg();
279   const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
280   const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
286   if (DstReg.isPhysical()) {
294       const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
323       getRegClass(MRI.getType(DstReg), DstRegBank);
341   const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
343     if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
774     MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
779       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
795   const Register DstReg = I.getOperand(0).getReg();
798   const LLT DstTy = MRI.getType(DstReg);
801   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
820     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
842       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
859   const Register DstReg = I.getOperand(0).getReg();
862   const LLT DstTy = MRI.getType(DstReg);
896         MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
900     DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
909       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
924   const Register DstReg = I.getOperand(0).getReg();
927   const LLT DstTy = MRI.getType(DstReg);
930   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
946     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
952       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
965       .addDef(DstReg)
1125   const Register DstReg = I.getOperand(0).getReg();
1134   const LLT DstTy = MRI.getType(DstReg);
1168   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1207       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1228   const Register DstReg = I.getOperand(0).getReg();
1232   const LLT DstTy = MRI.getType(DstReg);
1244     if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1279 bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
1283   const LLT DstTy = MRI.getType(DstReg);
1300   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1306       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1311   BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1317 bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
1321   const LLT DstTy = MRI.getType(DstReg);
1340   const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1343       !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1349       .addReg(DstReg, RegState::DefineNoRead, SubIdx)
1360   const Register DstReg = I.getOperand(0).getReg();
1365   const LLT DstTy = MRI.getType(DstReg);
1377     if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
1445   Register DstReg = I.getOperand(0).getReg();
1448   const LLT DstTy = MRI.getType(DstReg);
1452   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1477                                     TII.get(TargetOpcode::COPY), DstReg)
1519   const Register DstReg = I.getOperand(0).getReg();
1520   const LLT DstTy = MRI.getType(DstReg);
1521   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1548         addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1566         BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1582   Register DstReg = I.getOperand(0).getReg();
1584   if (!MRI.getRegClassOrNull(DstReg)) {
1585     const LLT DstTy = MRI.getType(DstReg);
1586     const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1588     if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1616   const Register DstReg = I.getOperand(0).getReg();
1620   const LLT RegTy = MRI.getType(DstReg);
1624   const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1748       !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
1816             DstReg)
1820             DstReg)
1832   unsigned DstReg = Sel.getReg(0);
1838   LLT Ty = MRI.getType(DstReg);
1856   BuildMI(*Sel.getParent(), Sel, Sel.getDebugLoc(), TII.get(OpCmp), DstReg)
1861   const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI);
1862   if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {