| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitConst32AndConst64.cpp | 77 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
84 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
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| H A D | HexagonCopyToCombine.cpp | 134 Register DestReg = Op0.getReg(); in isCombinableInstType() local
147 Register DestReg = Op0.getReg(); in isCombinableInstType() local
244 unsigned DestReg, in isUnsafeToMoveAcross()
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 63 emitThumb1LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb1LoadConstPool() argument
83 emitThumb2LoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,unsigned PredReg,unsigned MIFlags) emitThumb2LoadConstPool() argument
105 emitLoadConstPool(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,unsigned SubIdx,int Val,ARMCC::CondCodes Pred,Register PredReg,unsigned MIFlags) const emitLoadConstPool() argument
126 emitThumbRegPlusImmInReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,bool CanChangeCC,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags=MachineInstr::NoFlags) emitThumbRegPlusImmInReg() argument
253 emitThumbRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags) emitThumbRegPlusImmediate() argument
441 Register DestReg = MI.getOperand(0).getReg(); rewriteFrameIndex() local
466 Register DestReg = FrameReg; rewriteFrameIndex() local
[all...] |
| H A D | Thumb1InstrInfo.cpp | 44 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
145 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
[all...] |
| H A D | Thumb2InstrInfo.cpp | 211 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
135 Register DestReg = MI.getOperand(0).getReg(); optimizeSelect() local
153 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
311 emitT2RegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,ARMCC::CondCodes Pred,Register PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags) emitT2RegPlusImmediate() argument
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 794 emitLAInstSeq(MCRegister DestReg,MCRegister TmpReg,const MCExpr * Symbol,SmallVectorImpl<Inst> & Insts,SMLoc IDLoc,MCStreamer & Out,bool RelaxHint) emitLAInstSeq() argument
882 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressAbs() local
909 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressPcrel() local
931 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressPcrelLarge() local
955 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressGot() local
977 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressGotLarge() local
1001 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSLE() local
1019 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSIE() local
1041 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSIELarge() local
1065 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSLD() local
1087 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSLDLarge() local
1111 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSGD() local
1133 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSGDLarge() local
1167 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSDescAbs() local
1202 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSDescPcrel() local
1232 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadAddressTLSDescPcrelLarge() local
1256 MCRegister DestReg = Inst.getOperand(0).getReg(); emitLoadImm() local
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 152 Register DestReg = MI.getOperand(0).getReg(); doAtomicBinOpExpansion() local
219 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
243 Register DestReg = MI.getOperand(0).getReg(); doMaskedAtomicBinOpExpansion() local
381 Register DestReg = MI.getOperand(0).getReg(); expandAtomicMinMaxOp() local
496 Register DestReg = MI.getOperand(0).getReg(); expandAtomicCmpXchg() local
[all...] |
| H A D | LoongArchExpandPseudoInsts.cpp | 142 Register DestReg = MI.getOperand(0).getReg(); expandPcalau12iInstPair() local
204 Register DestReg = MI.getOperand(0).getReg(); expandLoadAddressTLSLE() local
293 Register DestReg = MI.getOperand(0).getReg(); expandLoadAddressTLSDesc() local
456 Register DestReg = MI.getOperand(0).getReg(); expandCopyCFR() local
499 expandLargeAddressLoad(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,MachineBasicBlock::iterator & NextMBBI,unsigned LastOpcode,unsigned IdentifyingMO,const MachineOperand & Symbol,Register DestReg,bool EraseFromParent) expandLargeAddressLoad() argument
635 Register DestReg = MI.getOperand(0).getReg(); expandLoadAddressTLSDescPcLarge() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPostRewrite.cpp | 82 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
103 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
157 Register DestReg = MI.getOperand(0).getReg(); in expandCondMove() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 390 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP() local
396 Register DestReg = createResultReg(RC); materializeFP() local
411 Register DestReg = createResultReg(RC); materializeGV() local
433 Register DestReg = createResultReg(RC); materializeExternalCallSym() local
1003 Register DestReg = createResultReg(&Mips::AFGR64RegClass); selectFPExt() local
1080 Register DestReg = createResultReg(&Mips::FGR32RegClass); selectFPTrunc() local
1118 Register DestReg = createResultReg(&Mips::GPR32RegClass); selectFPToInt() local
1594 Register DestReg = createResultReg(&Mips::GPR32RegClass); fastLowerIntrinsicCall() local
1722 Register DestReg = VA.getLocReg(); selectRet() local
1824 emitIntSExt32r1(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt32r1() argument
1843 emitIntSExt32r2(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt32r2() argument
1858 emitIntSExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntSExt() argument
1867 emitIntZExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg) emitIntZExt() argument
1889 emitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) emitIntExt() argument
1904 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); emitIntExt() local
2109 Register DestReg = createResultReg(&Mips::GPR32RegClass); simplifyAddress() local
[all...] |
| H A D | MipsInstrInfo.h | 146 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) loadRegFromStackSlot() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 265 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
301 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge()
330 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
470 Register DestReg = MI.getOperand(0).getReg(); in expandAtomicMinMaxOp() local
572 Register DestReg, Register CmpValReg, in tryToFoldBNEOnCmpXchgResult()
635 Register DestReg = MI.getOperand(0).getReg(); in expandAtomicCmpXchg() local
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| H A D | RISCVMergeBaseOffset.cpp | 304 Register DestReg = Lo.getOperand(0).getReg(); in detectAndFoldOffset() local
364 Register DestReg = Lo.getOperand(0).getReg(); in foldIntoMemoryOps() local
[all...] |
| H A D | RISCVExpandPseudoInsts.cpp | 195 Register DestReg = MI.getOperand(0).getReg(); expandCCOp() local
523 Register DestReg = MI.getOperand(0).getReg(); expandAuipcInstPair() local
588 Register DestReg = expandLoadTLSDescAddress() local
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| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.cpp | 146 return build(get(InstOpc), DestReg); in build() argument
149 build(unsigned InstOpc,Register DestReg) build() argument
264 Register DestReg = MI.getOperand(0).getReg(); processLDQ() local
334 Register DestReg = MI.getOperand(0).getReg(); processLDVM() local
420 Register DestReg = MI.getOperand(0).getReg(); processLDVM512() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
438 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
498 BuildMI(MachineBasicBlock * BB,const MIMetadata & MIMD,const MCInstrDesc & MCID,Register DestReg) BuildMI() argument
[all...] |
| /llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 92 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg() argument
64 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,Register DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
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| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
150 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineScheduler.cpp | 266 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind() local
353 Register DestReg = MI->getOperand(DstIndex).getReg(); AssignSlot() local
[all...] |
| H A D | AMDGPUMachineCFGStructurizer.cpp | |
| /llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.cpp | 107 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
133 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,Register DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 34 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 986 DestReg) in SelectFPTrunc() local
818 PPCEmitCmp(const Value * SrcValue1,const Value * SrcValue2,bool IsZExt,unsigned DestReg,const PPC::Predicate Pred) PPCEmitCmp() argument
1094 Register DestReg = createResultReg(&PPC::SPERCRegClass); SelectIToFP() local
1131 Register DestReg = createResultReg(RC); SelectIToFP() local
1223 unsigned DestReg; SelectFPToI() local
1808 PPCEmitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,unsigned DestReg,bool IsZExt) PPCEmitIntExt() argument
2006 Register DestReg = createResultReg(RC); PPCMaterializeFP() local
2062 Register DestReg = createResultReg(RC); PPCMaterializeGV() local
[all...] |
| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 44 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg() argument
166 loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,Register DestReg,int FrameIndex,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI,Register VReg) const loadRegFromStackSlot() argument
[all...] |
| /llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.cpp | 437 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
480 copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const copyPhysReg() argument
[all...] |