Lines Matching defs:DestReg

134     Register DestReg = MI.getOperand(0).getReg();
136     if (!DestReg.isVirtual())
140                                         get(ARM::t2CSEL), DestReg)
152                                   const DebugLoc &DL, MCRegister DestReg,
156   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
157     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
159   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
211     MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
223     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
235     if (DestReg.isVirtual()) {
237       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
241     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
242     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
245     if (DestReg.isPhysical())
246       MIB.addReg(DestReg, RegState::ImplicitDefine);
250   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI,
313                                   const DebugLoc &dl, Register DestReg,
318   if (NumBytes == 0 && DestReg != BaseReg) {
319     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
330   if (DestReg != ARM::SP && DestReg != BaseReg &&
336       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
342       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
343         .addReg(DestReg)
351         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
353             .addReg(DestReg, RegState::Kill)
358         // Here we know that DestReg is not SP but we do not
363         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
365             .addReg(DestReg, RegState::Kill)
377     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
379       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
387     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
391     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
394       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
403     bool ToSP = DestReg == ARM::SP;
429     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
437     BaseReg = DestReg;