[LoongArch] Emit R_LARCH_RELAX when expanding some macros (#120067)

Emit `R_LARCH_RELAX` relocations when expanding some macros, including:

- `la.tls.ie`, `la.tls.ld`, `la.tls.gd`, `la.tls.desc`,

[LoongArch] Emit R_LARCH_RELAX when expanding some macros (#120067)

Emit `R_LARCH_RELAX` relocations when expanding some macros, including:

- `la.tls.ie`, `la.tls.ld`, `la.tls.gd`, `la.tls.desc`,
- `call36`, `tail36`.

Other macros that need to emit `R_LARCH_RELAX` relocations was
implemented in https://github.com/llvm/llvm-project/pull/72961, including:

- `la.local`, `la.pcrel`, `la.pcrel` expanded as `la.abs`, `la`,
`la.global`, `la/la.global` expanded as `la.pcrel`, `la.got`.

Note: `la.tls.le` macro can be relaxed when expanded with
`R_LARCH_TLS_LE_{HI20/ADD/LO12}_R` relocations. But if we do so,
previously handwritten assembly code will occur error due to the
redundant `add.{w/d}` followed by `la.tls.le`. So `la.tls.le` keeps to
expands with `R_LARCH_TLS_LE_{HI20/LO12}`.

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[LoongArch] Support parsing register names in CFI instructions

Reviewed By: MQ-mengqing, heiher, xen0n

Pull Request: https://github.com/llvm/llvm-project/pull/117120

[LoongArch] Record the special AMO operand constraint with TableGen (#114398)

Depends on #114508

The LoongArch Reference Manual says that the 3-register atomic memory
operations cannot have thei

[LoongArch] Record the special AMO operand constraint with TableGen (#114398)

Depends on #114508

The LoongArch Reference Manual says that the 3-register atomic memory
operations cannot have their rd equal to either rj or rk [^1], and both
GNU as and LLVM IAS enforce the constraint for non-zero rd. However,
currently LoongArch AsmParser is checking for the opcode with a direct
numerical comparison on the opcode, which is enum-typed: the fact that
all AMO insns have adjacent numerical values is merely a coincidence,
and it is better to not rely on the current TableGen implementation
behavior.

Instead, start to leverage the target-specific flags field of
MCInstrDesc, and record the constraint with TableGen, so we can stop
treating the opcode value as number. In doing so, we also have to mark
whether the instruction is AMCAS, because the operand index of rj and rk
for the AMCAS instructions is different.

While documenting the new flag, it was found that v1.10 of the Manual
did not specify the similar constraint for the AMCAS instructions.
Experiments were done on a Loongson 3A6000 (LA664 uarch) and it turned
out that at least AMCAS will still signal INE with `rd == rj`. The `rd
== rk` case should be a no-op according to the semantics, but as it is
meaningless to perform CAS with the "old value" same as the "new value",
it is not worth special-casing. So the current behavior of also
enforcing the constraint for AMCAS is kept.

[^1]: if `rd == rj` an INE would be signaled; if `rd == rk` it is UB.

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[LoongArch][NFC] Fix the operand constraint of AMCAS instructions (#114508)

The `rd` operand of AMCAS instructions is both read and written, because
of the nature of compare-and-swap operations, bu

[LoongArch][NFC] Fix the operand constraint of AMCAS instructions (#114508)

The `rd` operand of AMCAS instructions is both read and written, because
of the nature of compare-and-swap operations, but currently it is not
declared as such. Fix it for upcoming codegen enablement changes. In
order to do that, a piece of LoongArchAsmParser logic that relied on
TableGen-erated enum variants being ordered in a specific way needs
updating; this will be addressed in a following refactor. No functional
change intended.

While at it, restore vertical alignment for the definition lines.

Suggested-by: tangaac <tangyan01@loongson.cn>
Link:
https://github.com/llvm/llvm-project/pull/114398#discussion_r1825362676

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[LoongArch][MC] Handle more PseudoLA* instructions with la-global-with-abs feature

This is to align with GAS. Additionally, there are some minor changes:
the definition and expansion process of the

[LoongArch][MC] Handle more PseudoLA* instructions with la-global-with-abs feature

This is to align with GAS. Additionally, there are some minor changes:
the definition and expansion process of the TLS_DESC pseudo-instruction
were modified in the same style.

Reviewed By: heiher

Pull Request: https://github.com/llvm/llvm-project/pull/112858

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[LoongArch] Support .option directive

The .option can accept 4 parameters like the LoongArch's gnu as:
push, pop, relax and norelax.

Reviewed By: heiher, SixWeining

Pull Request: https://github.co

[LoongArch] Support .option directive

The .option can accept 4 parameters like the LoongArch's gnu as:
push, pop, relax and norelax.

Reviewed By: heiher, SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/110404

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[LoongArch] Use MCRegister. NFC

[NFC] Update function names in MCTargetAsmParser.h (#108643)

Update function names to adhere to LLVM coding standard.

[LoongArch] Optimize for immediate value materialization using BSTRINS_D instruction

Reviewed By: heiher, SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/106332

[MC] Update MCOperand::getReg/setReg/createReg and MCInstBuilder::addReg to use MCRegister. (#106015)

Replace unsigned with MCRegister.

Update some ternary operators that started giving errors.

[LoongArch][MC] Support %[ld_/gd_/desc_]pcrel_20

Reviewed By: SixWeining, MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/100104

[LoongArch] Support parsing the `%le_{hi20,add,lo12}_r` modifiers

Reviewed By: SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/99485

[LoongArch] Support parsing la.tls.desc pseudo instruction

Simultaneously implemented parsing support for the `%desc_*` modifiers.

Reviewers: SixWeining, heiher, xen0n

Reviewed By: xen0n, SixWeini

[LoongArch] Support parsing la.tls.desc pseudo instruction

Simultaneously implemented parsing support for the `%desc_*` modifiers.

Reviewers: SixWeining, heiher, xen0n

Reviewed By: xen0n, SixWeining

Pull Request: https://github.com/llvm/llvm-project/pull/90158

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[MC] Make `MCParsedAsmOperand::getReg()` return `MCRegister` (#86444)

[LoongArch] Add diagnostics for PseudoLI_D instruction (#85742)

Simultaneously improved diagnostic testing for the `PseudoLI_W`
instruction.

[LoongArch] Emit function call code sequence as `PCADDU18I+JIRL` in medium code model

According to the description of the psABI v2.20:
https://github.com/loongson/la-abi-specs/releases/tag/v2.20, ad

[LoongArch] Emit function call code sequence as `PCADDU18I+JIRL` in medium code model

According to the description of the psABI v2.20:
https://github.com/loongson/la-abi-specs/releases/tag/v2.20, adjustments
are made to the function call instructions under the medium code model.

At the same time, AsmParser has already supported parsing the call36 and
tail36 macro instructions.

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[LoongArch] Emit R_LARCH_RELAX when expanding some LoadAddress (#72961)

Emit relax relocs when expand non-large la.pcrel and non-large la.got on
llvm-mc stage, which like what does on GAS.
1, la.p

[LoongArch] Emit R_LARCH_RELAX when expanding some LoadAddress (#72961)

Emit relax relocs when expand non-large la.pcrel and non-large la.got on
llvm-mc stage, which like what does on GAS.
1, la.pcrel -> PCALA_HI20 + RELAX + PCALA_LO12 + RELAX
2, la.got -> GOT_PC_HI20 + RELAX + GOT_PC_LO12 + RELAX

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[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variab

[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).

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[LoongArch] Add definition for LVZ/LBT instructions

This patch defines the `LVZ` and `LBT` extension instructions, which
provide enough definitions for llvm-mc and llvm-objdump to correctly
handle t

[LoongArch] Add definition for LVZ/LBT instructions

This patch defines the `LVZ` and `LBT` extension instructions, which
provide enough definitions for llvm-mc and llvm-objdump to correctly
handle these instructions.

It also defines the `SCR` (Scratchpad Register) register class, which
are used by the `LBT` extension instructions.

Reviewed By: SixWeining, xen0n

Differential Revision: https://reviews.llvm.org/D155917

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[LoongArch] Add definition for LSX instructions

This patch adds the definition for the `LSX` registers and instructions.
It also adds handling for new immediate operands in the AsmParser. This
patch

[LoongArch] Add definition for LSX instructions

This patch adds the definition for the `LSX` registers and instructions.
It also adds handling for new immediate operands in the AsmParser. This
patch ensures that llvm-mc and llvm-objdump correctly handle the `LSX`
instructions.

We expand those pseudo-instructions `vrepli.{b,h,w,d}` in the
MCCodeEmitter. This increases the readability of the output when
generating assembly files.

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D154183

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[MC/AsmParser] Remove no-op overrides of parseDirective (NFC)

Remove overrides of parseDirective that unconditionally return NoMatch.
This is what the base implementation does.

This is a follow-up

[MC/AsmParser] Remove no-op overrides of parseDirective (NFC)

Remove overrides of parseDirective that unconditionally return NoMatch.
This is what the base implementation does.

This is a follow-up to D154101 based on post-commit review feedback.

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[LoongArch] Replace OperandMatchResultTy with ParseStatus (NFC)

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return E

[LoongArch] Replace OperandMatchResultTy with ParseStatus (NFC)

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
Error(L, "msg");
return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.

Reviewed By: xen0n

Differential Revision: https://reviews.llvm.org/D154318

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[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third sta

[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third state: the
directive is not target specific. AsmParser::parseStatement detected
this case by using a fragile heuristic: if the target parser did not
consume any tokens, the directive is assumed to be not target-specific.

Some targets fail to follow the convention: they return success after
emitting an error or do not consume the entire line and return failure
on successful parsing. This was partially worked around by checking for
pending errors in parseStatement.

This patch tries to improve the situation by introducing parseDirective
method that returns ParseStatus -- three-state class. The new method
should eventually replace the old one returning bool.

ParseStatus is intentionally implicitly constructible from bool to allow
uses like `return Error(Loc, "message")`. It also has a potential to
replace OperandMatchResulTy as it is more convenient to use due to the
implicit construction from bool and more type safe.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D154101

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[LoongArch] Use parseOptionalToken. NFC

[LoongArch] Handle out-fo-range uimm8 operands in LoongArchAsmParser

With this fix, when encountering an out-of-range uimm8 operand, the code
now triggers an appropriate error message, clearly indic

[LoongArch] Handle out-fo-range uimm8 operands in LoongArchAsmParser

With this fix, when encountering an out-of-range uimm8 operand, the code
now triggers an appropriate error message, clearly indicating that the
immediate value must be an integer within the range of 0 to 255.

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