Lines Matching defs:DestReg

178   bool emitCmp(unsigned DestReg, const CmpInst *CI);
182   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
187   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189                        unsigned DestReg);
191                        unsigned DestReg);
388     Register DestReg = createResultReg(RC);
390     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
391     return DestReg;
394     Register DestReg = createResultReg(RC);
398     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
399     return DestReg;
409   Register DestReg = createResultReg(RC);
415   emitInst(Mips::LW, DestReg)
422         .addReg(DestReg)
424     DestReg = TempReg;
426   return DestReg;
431   Register DestReg = createResultReg(RC);
432   emitInst(Mips::LW, DestReg)
435   return DestReg;
1015   Register DestReg = createResultReg(&Mips::AFGR64RegClass);
1016   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1017   updateValueMap(I, DestReg);
1092   Register DestReg = createResultReg(&Mips::FGR32RegClass);
1093   if (!DestReg)
1096   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1097   updateValueMap(I, DestReg);
1130   Register DestReg = createResultReg(&Mips::GPR32RegClass);
1136   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1138   updateValueMap(I, DestReg);
1606     Register DestReg = createResultReg(&Mips::GPR32RegClass);
1607     if (DestReg == 0)
1611         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1612         updateValueMap(II, DestReg);
1624         emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
1625         updateValueMap(II, DestReg);
1632         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1633         updateValueMap(II, DestReg);
1653         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1654         updateValueMap(II, DestReg);
1734     Register DestReg = VA.getLocReg();
1736     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1772             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1836                                    unsigned DestReg) {
1850   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1855                                    unsigned DestReg) {
1860     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1863     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1870                                unsigned DestReg) {
1874     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1875   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1879                                unsigned DestReg) {
1896   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1901                               unsigned DestReg, bool IsZExt) {
1910     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1911   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1916   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1917   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1918   return Success ? DestReg : 0;
2121     Register DestReg = createResultReg(&Mips::GPR32RegClass);
2122     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2123     Addr.setReg(DestReg);