[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new pr

[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture. Once new systems become available, the
official system name will be added as supported -march name.

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[SystemZ] Fix address parsing in HLASM mode

When parsing an address that contains only a single register
for an instruction that actually has both a base and an index
register, the parsed register i

[SystemZ] Fix address parsing in HLASM mode

When parsing an address that contains only a single register
for an instruction that actually has both a base and an index
register, the parsed register is treated as base by AsmParser.

This is correct when emulating the GNU assembler, but not when
emulating HLASM, as the latter treat the register as index in
this case.

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[SystemZ] Fix address operand parsing incompatibilities with GAS

The LLVM AsmParser showed different behavior compared to GAS when
parsing address operands in the following two ways:

- If the addre

[SystemZ] Fix address operand parsing incompatibilities with GAS

The LLVM AsmParser showed different behavior compared to GAS when
parsing address operands in the following two ways:

- If the address operand only has a single register (no comma),
it is always interpreted as base register by GAS, even in the
vector-index case (vgef etc.) This means the following is
actually incorrect usage, as the base cannot be a vector
register: vgef %v0, 0(%v1), 0.

- GAS allows specifying a missing base register by using a
comma after the first register, e.g. vgef %v0, 0(%v1,), 0.

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[SystemZ] Split SystemZInstPrinter to two classes based on Asm dialect (#112975)

In preparation for future work on separating the output of the GNU/HLASM
ASM dialects, we first separate the SystemZ

[SystemZ] Split SystemZInstPrinter to two classes based on Asm dialect (#112975)

In preparation for future work on separating the output of the GNU/HLASM
ASM dialects, we first separate the SystemZInstPrinter classes to two
versions, one for each ASM dialect.

The common code remains in a SystemZInstPrinterCommon class instead.

---------

Co-authored-by: Tony Tao <tonytao@ca.ibm.com>

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[SystemZ] Rename SystemZ ATT Asm dialect to GNU Asm dialect (#112800)

The ATT assembler dialect on SystemZ seems to have been taken from the
existing ATT/Intel code. However, on SystemZ, ATT does n

[SystemZ] Rename SystemZ ATT Asm dialect to GNU Asm dialect (#112800)

The ATT assembler dialect on SystemZ seems to have been taken from the
existing ATT/Intel code. However, on SystemZ, ATT does not hold any
meaning. In reality, we are splitting the difference between GNU Asm
syntax and HLASM Asm syntax, so it makes sense to rename ATT to GNU
instead.

Co-authored-by: Tony Tao <tonytao@ca.ibm.com>

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[NFC] Update function names in MCTargetAsmParser.h (#108643)

Update function names to adhere to LLVM coding standard.

[llvm][SystemZ] Fix parsing of `.cfi_undefined` with percent-less registers. (#107032)

This is just e3d658b applied to SystemZ.

An example of this being used in the wild:
https://sourceware.org/

[llvm][SystemZ] Fix parsing of `.cfi_undefined` with percent-less registers. (#107032)

This is just e3d658b applied to SystemZ.

An example of this being used in the wild:
https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/s390/s390-64/start.S;h=59eeb7e998227bdf32029cd074f0876c450404ea;hb=HEAD#l63

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[MC] Make `MCParsedAsmOperand::getReg()` return `MCRegister` (#86444)

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.

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[SystemZ] Handle index-only addresses in (dis)assembler

Most addresses in SystemZ instructions take two registers,
an index register and a base register. However, either of
those can be omitted. I

[SystemZ] Handle index-only addresses in (dis)assembler

Most addresses in SystemZ instructions take two registers,
an index register and a base register. However, either of
those can be omitted. If there is just a single register,
this usually is taken as the base register - however, there
are certain rare cases where you specifically want to use
an index register but no base register. This is currently
not handled consistently by the assembler / disassembler.

Fix this by
- always emitting a dummy 0 as base register for index-
only addresses
- correctly handle dummy 0 as indicating no base register
when parsing an address

This is compatible with current GNU binutils behavior.

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[SystemZ][NFC] Fix a couple of style issues (#69958)

Some fixes for style issues pointed out by clang-tidy:

- Upper case/lower case fixes
- No else after return
- Removed unused #include's
- A

[SystemZ][NFC] Fix a couple of style issues (#69958)

Some fixes for style issues pointed out by clang-tidy:

- Upper case/lower case fixes
- No else after return
- Removed unused #include's
- Added NOLINTNEXTLINE() for the LLVM* functions

All changes are NFC.

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[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variab

[MC] Change tryParseRegister to return ParseStatus (NFC)

This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).

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[SystemZ] Replace OperandMatchResultTy with ParseStatus (NFC)

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Err

[SystemZ] Replace OperandMatchResultTy with ParseStatus (NFC)

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
Error(L, "msg");
return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D154316

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[SystemZ] Allow symbols in immediate asm operands

Currently mentioning any symbols in immediate asm operands is not
supported, for example:

error: invalid operand for instruction
lghi %r4,f

[SystemZ] Allow symbols in immediate asm operands

Currently mentioning any symbols in immediate asm operands is not
supported, for example:

error: invalid operand for instruction
lghi %r4,foo_end-foo

The immediate problem is that is*Imm() and print*Operand() functions do
not accept MCExprs, but simply relaxing these checks is not enough:
after symbol addresses are computed, range checks need to run against
resolved values.

Add a number of SystemZ::FixupKind members for each kind of immediate
value and process them in SystemZMCAsmBackend::applyFixup(). Only
perform the range checks, do not change anything.

Adjust the tests: move previously failing cases like the one shown
above out of insn-bad.s.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D154899

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[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third sta

[MC] Add three-state parseDirective as a replacement for ParseDirective

Conventionally, parsing methods return false on success and true on
error. However, directive parsing methods need a third state: the
directive is not target specific. AsmParser::parseStatement detected
this case by using a fragile heuristic: if the target parser did not
consume any tokens, the directive is assumed to be not target-specific.

Some targets fail to follow the convention: they return success after
emitting an error or do not consume the entire line and return failure
on successful parsing. This was partially worked around by checking for
pending errors in parseStatement.

This patch tries to improve the situation by introducing parseDirective
method that returns ParseStatus -- three-state class. The new method
should eventually replace the old one returning bool.

ParseStatus is intentionally implicitly constructible from bool to allow
uses like `return Error(Loc, "message")`. It also has a potential to
replace OperandMatchResulTy as it is more convenient to use due to the
implicit construction from bool and more type safe.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D154101

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[llvm] Add missing StringExtras.h includes

In preparation for removing the `#include "llvm/ADT/StringExtras.h"`
from the header to source file of `llvm/Support/Error.h`, first add in
all the missing

[llvm] Add missing StringExtras.h includes

In preparation for removing the `#include "llvm/ADT/StringExtras.h"`
from the header to source file of `llvm/Support/Error.h`, first add in
all the missing includes that were previously included transitively
through this header.

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Drop U6Imm-related definitions

They are no longer used, which leads to the -Wunused-function warning.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D147521

[MC] Use `MCRegister` instead of `unsigned` in `MCTargetAsmParser`

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D140273

[SystemZ] Emit a .gnu_attribute for an externally visible vector abi.

On SystemZ, the vector ABI changes depending on the presence of hardware
vector support. Therefore, each binary compiled with a

[SystemZ] Emit a .gnu_attribute for an externally visible vector abi.

On SystemZ, the vector ABI changes depending on the presence of hardware
vector support. Therefore, each binary compiled with a visible vector ABI
(e.g. one that calls an external function with a vector argument) should be
marked with a .gnu_attribute describing this.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D105067

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[SystemZ] Accept (. - 0x100000000) PCRel32 constants

Clang does not accept instructions like brasl %r0,.-0x100000000,
because the second operand's right-hand-side (0x100000000) barely
misses the acc

[SystemZ] Accept (. - 0x100000000) PCRel32 constants

Clang does not accept instructions like brasl %r0,.-0x100000000,
because the second operand's right-hand-side (0x100000000) barely
misses the acceptable range. However, since it's being subtracted, it
makes sense to perform the range check on the negated value.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D124780

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Cleanup MCParser headers

As usual with that header cleanup series, some implicit dependencies now need to
be explicit:

llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.

Cleanup MCParser headers

As usual with that header cleanup series, some implicit dependencies now need to
be explicit:

llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.h

Preprocessed lines to build llvm on my setup:
after: 1068185081
before: 1068324320

So no compile time benefit to expect, but we still get the looser coupling
between files which is great.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D119359

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[SystemZ] Support symbolic displacements.

This patch adds support for symbolic displacements, e.g. like 'lg %r0,
sym(%r1)', which is done using relocations. This is needed to compile the
kernel with

[SystemZ] Support symbolic displacements.

This patch adds support for symbolic displacements, e.g. like 'lg %r0,
sym(%r1)', which is done using relocations. This is needed to compile the
kernel without disabling the integrated assembler.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D113341

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Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

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[SystemZ] Remove redundant declaration SystemZMnemonicSpellCheck (NFC)

Note that SystemZMnemonicSpellCheck is defined in
SystemZGenAsmMatcher.inc, which SystemZAsmParser.cpp includes.

Identified wi

[SystemZ] Remove redundant declaration SystemZMnemonicSpellCheck (NFC)

Note that SystemZMnemonicSpellCheck is defined in
SystemZGenAsmMatcher.inc, which SystemZAsmParser.cpp includes.

Identified with readability-redundant-declaration.

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[SystemZ] Recognize .machine directive in parser.

The .machine directive can be used in assembly files to specify the ISA for
the instructions following it.

Review: Ulrich Weigand
Differential Rev

[SystemZ] Recognize .machine directive in parser.

The .machine directive can be used in assembly files to specify the ISA for
the instructions following it.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D109660

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