Replace some bit operations with simpler ones. No functionality change.

llvm-svn: 182226

The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of

The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.

llvm-svn: 181705

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ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod

ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.

Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.

This commit adds a proper diagnostic message for Imm0_4 and updates all tests.

Patch by Mihail Popa <Mihail.Popa@arm.com>.

llvm-svn: 180617

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ARM: Permit "sp" in ARM variant of STREXD instructions

Patch from Mihail Popa

llvm-svn: 179854

ARM: permit "sp" in ARM variants of MOVW/MOVT instructions

llvm-svn: 179847

Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wf

Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)

Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.

Patch by Mihail Popa <Mihail.Popa@arm.com>

llvm-svn: 179707

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Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended. Added test case.

llvm-svn: 178275

Patch by Gordon Keiser!

If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.

This patch addresses failure to

Patch by Gordon Keiser!

If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.

This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.

llvm-svn: 178017

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Remove edis - the enhanced disassembler. Fixes PR14654.

llvm-svn: 170578

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131

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Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
which would then cause an assert when printed. rdar://11437956

llvm-svn: 168960

Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to

Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.

llvm-svn: 166982

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Fix a bug where a 32-bit address with the high bit does not get symbolicated
because the value is incorrectly being signed extended when passed to
SymbolLookUp().

llvm-svn: 166234

Fix the handling of edge cases in ARM shifted operands.

This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris L

Fix the handling of edge cases in ARM shifted operands.

This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455

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Diagnose invalid alignments on duplicating VLDn instructions.

Patch by Chris Lidbury.

llvm-svn: 163323

Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.

Patch by Chris Lidbury.

llvm-svn: 163321

Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.

llvm-svn: 162623

Remove unnecessary include of ARMGenInstrInfo.inc.

llvm-svn: 162086

Switch the fixed-length disassembler to be table-driven.

Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() stat

Switch the fixed-length disassembler to be table-driven.

Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s

TEXT size:
Previous: 447,251
New: 297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888

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Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.

llvm-svn: 161162

Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.

llvm-svn: 161161

Fix a typo (the the => the)

llvm-svn: 160621

Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!

llvm-svn: 159989

Revert r159938 (and r159945) to appease the buildbots.

llvm-svn: 159960

Oops - correct broken disassembly for VMOV

llvm-svn: 159945