1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "llvm/MC/EDInstInfo.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/LEB128.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <vector> 30 31 using namespace llvm; 32 33 typedef MCDisassembler::DecodeStatus DecodeStatus; 34 35 namespace { 36 // Handles the condition code status of instructions in IT blocks 37 class ITStatus 38 { 39 public: 40 // Returns the condition code for instruction in IT block 41 unsigned getITCC() { 42 unsigned CC = ARMCC::AL; 43 if (instrInITBlock()) 44 CC = ITStates.back(); 45 return CC; 46 } 47 48 // Advances the IT block state to the next T or E 49 void advanceITState() { 50 ITStates.pop_back(); 51 } 52 53 // Returns true if the current instruction is in an IT block 54 bool instrInITBlock() { 55 return !ITStates.empty(); 56 } 57 58 // Returns true if current instruction is the last instruction in an IT block 59 bool instrLastInITBlock() { 60 return ITStates.size() == 1; 61 } 62 63 // Called when decoding an IT instruction. Sets the IT state for the following 64 // instructions that for the IT block. Firstcond and Mask correspond to the 65 // fields in the IT instruction encoding. 66 void setITState(char Firstcond, char Mask) { 67 // (3 - the number of trailing zeros) is the number of then / else. 68 unsigned CondBit0 = Firstcond & 1; 69 unsigned NumTZ = CountTrailingZeros_32(Mask); 70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 71 assert(NumTZ <= 3 && "Invalid IT mask!"); 72 // push condition codes onto the stack the correct order for the pops 73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 74 bool T = ((Mask >> Pos) & 1) == CondBit0; 75 if (T) 76 ITStates.push_back(CCBits); 77 else 78 ITStates.push_back(CCBits ^ 1); 79 } 80 ITStates.push_back(CCBits); 81 } 82 83 private: 84 std::vector<unsigned char> ITStates; 85 }; 86 } 87 88 namespace { 89 /// ARMDisassembler - ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 /// Constructor - Initializes the disassembler. 93 /// 94 ARMDisassembler(const MCSubtargetInfo &STI) : 95 MCDisassembler(STI) { 96 } 97 98 ~ARMDisassembler() { 99 } 100 101 /// getInstruction - See MCDisassembler. 102 DecodeStatus getInstruction(MCInst &instr, 103 uint64_t &size, 104 const MemoryObject ®ion, 105 uint64_t address, 106 raw_ostream &vStream, 107 raw_ostream &cStream) const; 108 109 /// getEDInfo - See MCDisassembler. 110 const EDInstInfo *getEDInfo() const; 111 private: 112 }; 113 114 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 115 class ThumbDisassembler : public MCDisassembler { 116 public: 117 /// Constructor - Initializes the disassembler. 118 /// 119 ThumbDisassembler(const MCSubtargetInfo &STI) : 120 MCDisassembler(STI) { 121 } 122 123 ~ThumbDisassembler() { 124 } 125 126 /// getInstruction - See MCDisassembler. 127 DecodeStatus getInstruction(MCInst &instr, 128 uint64_t &size, 129 const MemoryObject ®ion, 130 uint64_t address, 131 raw_ostream &vStream, 132 raw_ostream &cStream) const; 133 134 /// getEDInfo - See MCDisassembler. 135 const EDInstInfo *getEDInfo() const; 136 private: 137 mutable ITStatus ITBlock; 138 DecodeStatus AddThumbPredicate(MCInst&) const; 139 void UpdateThumbVFPPredicate(MCInst&) const; 140 }; 141 } 142 143 static bool Check(DecodeStatus &Out, DecodeStatus In) { 144 switch (In) { 145 case MCDisassembler::Success: 146 // Out stays the same. 147 return true; 148 case MCDisassembler::SoftFail: 149 Out = In; 150 return true; 151 case MCDisassembler::Fail: 152 Out = In; 153 return false; 154 } 155 llvm_unreachable("Invalid DecodeStatus!"); 156 } 157 158 159 // Forward declare these because the autogenerated code will reference them. 160 // Definitions are further down. 161 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 164 unsigned RegNo, uint64_t Address, 165 const void *Decoder); 166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Address, 181 const void *Decoder); 182 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 187 unsigned RegNo, uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 203 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 208 unsigned Insn, 209 uint64_t Address, 210 const void *Decoder); 211 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 220 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 221 unsigned Insn, 222 uint64_t Adddress, 223 const void *Decoder); 224 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 319 320 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 383 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 #include "ARMGenDisassemblerTables.inc" 388 #include "ARMGenEDInfo.inc" 389 390 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 391 return new ARMDisassembler(STI); 392 } 393 394 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 395 return new ThumbDisassembler(STI); 396 } 397 398 const EDInstInfo *ARMDisassembler::getEDInfo() const { 399 return instInfoARM; 400 } 401 402 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 403 return instInfoARM; 404 } 405 406 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 407 const MemoryObject &Region, 408 uint64_t Address, 409 raw_ostream &os, 410 raw_ostream &cs) const { 411 CommentStream = &cs; 412 413 uint8_t bytes[4]; 414 415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 417 418 // We want to read exactly 4 bytes of data. 419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 420 Size = 0; 421 return MCDisassembler::Fail; 422 } 423 424 // Encoded as a small-endian 32-bit word in the stream. 425 uint32_t insn = (bytes[3] << 24) | 426 (bytes[2] << 16) | 427 (bytes[1] << 8) | 428 (bytes[0] << 0); 429 430 // Calling the auto-generated decoder function. 431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 432 Address, this, STI); 433 if (result != MCDisassembler::Fail) { 434 Size = 4; 435 return result; 436 } 437 438 // VFP and NEON instructions, similarly, are shared between ARM 439 // and Thumb modes. 440 MI.clear(); 441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 442 if (result != MCDisassembler::Fail) { 443 Size = 4; 444 return result; 445 } 446 447 MI.clear(); 448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 449 this, STI); 450 if (result != MCDisassembler::Fail) { 451 Size = 4; 452 // Add a fake predicate operand, because we share these instruction 453 // definitions with Thumb2 where these instructions are predicable. 454 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 455 return MCDisassembler::Fail; 456 return result; 457 } 458 459 MI.clear(); 460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 461 this, STI); 462 if (result != MCDisassembler::Fail) { 463 Size = 4; 464 // Add a fake predicate operand, because we share these instruction 465 // definitions with Thumb2 where these instructions are predicable. 466 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 467 return MCDisassembler::Fail; 468 return result; 469 } 470 471 MI.clear(); 472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 473 this, STI); 474 if (result != MCDisassembler::Fail) { 475 Size = 4; 476 // Add a fake predicate operand, because we share these instruction 477 // definitions with Thumb2 where these instructions are predicable. 478 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 479 return MCDisassembler::Fail; 480 return result; 481 } 482 483 MI.clear(); 484 485 Size = 0; 486 return MCDisassembler::Fail; 487 } 488 489 namespace llvm { 490 extern const MCInstrDesc ARMInsts[]; 491 } 492 493 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 494 /// immediate Value in the MCInst. The immediate Value has had any PC 495 /// adjustment made by the caller. If the instruction is a branch instruction 496 /// then isBranch is true, else false. If the getOpInfo() function was set as 497 /// part of the setupForSymbolicDisassembly() call then that function is called 498 /// to get any symbolic information at the Address for this instruction. If 499 /// that returns non-zero then the symbolic information it returns is used to 500 /// create an MCExpr and that is added as an operand to the MCInst. If 501 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 502 /// Value is done and if a symbol is found an MCExpr is created with that, else 503 /// an MCExpr with Value is created. This function returns true if it adds an 504 /// operand to the MCInst and false otherwise. 505 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 506 bool isBranch, uint64_t InstSize, 507 MCInst &MI, const void *Decoder) { 508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 510 struct LLVMOpInfo1 SymbolicOp; 511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 512 SymbolicOp.Value = Value; 513 void *DisInfo = Dis->getDisInfoBlock(); 514 515 if (!getOpInfo || 516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 517 // Clear SymbolicOp.Value from above and also all other fields. 518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 520 if (!SymbolLookUp) 521 return false; 522 uint64_t ReferenceType; 523 if (isBranch) 524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 525 else 526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 527 const char *ReferenceName; 528 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 529 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 530 Address, &ReferenceName); 531 if (Name) { 532 SymbolicOp.AddSymbol.Name = Name; 533 SymbolicOp.AddSymbol.Present = true; 534 } 535 // For branches always create an MCExpr so it gets printed as hex address. 536 else if (isBranch) { 537 SymbolicOp.Value = Value; 538 } 539 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 540 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 541 if (!Name && !isBranch) 542 return false; 543 } 544 545 MCContext *Ctx = Dis->getMCContext(); 546 const MCExpr *Add = NULL; 547 if (SymbolicOp.AddSymbol.Present) { 548 if (SymbolicOp.AddSymbol.Name) { 549 StringRef Name(SymbolicOp.AddSymbol.Name); 550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 551 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 552 } else { 553 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 554 } 555 } 556 557 const MCExpr *Sub = NULL; 558 if (SymbolicOp.SubtractSymbol.Present) { 559 if (SymbolicOp.SubtractSymbol.Name) { 560 StringRef Name(SymbolicOp.SubtractSymbol.Name); 561 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 562 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 563 } else { 564 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 565 } 566 } 567 568 const MCExpr *Off = NULL; 569 if (SymbolicOp.Value != 0) 570 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 571 572 const MCExpr *Expr; 573 if (Sub) { 574 const MCExpr *LHS; 575 if (Add) 576 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 577 else 578 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 579 if (Off != 0) 580 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 581 else 582 Expr = LHS; 583 } else if (Add) { 584 if (Off != 0) 585 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 586 else 587 Expr = Add; 588 } else { 589 if (Off != 0) 590 Expr = Off; 591 else 592 Expr = MCConstantExpr::Create(0, *Ctx); 593 } 594 595 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 596 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 597 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 598 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 599 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 600 MI.addOperand(MCOperand::CreateExpr(Expr)); 601 else 602 llvm_unreachable("bad SymbolicOp.VariantKind"); 603 604 return true; 605 } 606 607 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 608 /// referenced by a load instruction with the base register that is the Pc. 609 /// These can often be values in a literal pool near the Address of the 610 /// instruction. The Address of the instruction and its immediate Value are 611 /// used as a possible literal pool entry. The SymbolLookUp call back will 612 /// return the name of a symbol referenced by the literal pool's entry if 613 /// the referenced address is that of a symbol. Or it will return a pointer to 614 /// a literal 'C' string if the referenced address of the literal pool's entry 615 /// is an address into a section with 'C' string literals. 616 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 617 const void *Decoder) { 618 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 619 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 620 if (SymbolLookUp) { 621 void *DisInfo = Dis->getDisInfoBlock(); 622 uint64_t ReferenceType; 623 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 624 const char *ReferenceName; 625 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 626 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 627 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 628 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 629 } 630 } 631 632 // Thumb1 instructions don't have explicit S bits. Rather, they 633 // implicitly set CPSR. Since it's not represented in the encoding, the 634 // auto-generated decoder won't inject the CPSR operand. We need to fix 635 // that as a post-pass. 636 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 639 MCInst::iterator I = MI.begin(); 640 for (unsigned i = 0; i < NumOps; ++i, ++I) { 641 if (I == MI.end()) break; 642 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 643 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 644 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 645 return; 646 } 647 } 648 649 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 650 } 651 652 // Most Thumb instructions don't have explicit predicates in the 653 // encoding, but rather get their predicates from IT context. We need 654 // to fix up the predicate operands using this context information as a 655 // post-pass. 656 MCDisassembler::DecodeStatus 657 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 658 MCDisassembler::DecodeStatus S = Success; 659 660 // A few instructions actually have predicates encoded in them. Don't 661 // try to overwrite it if we're seeing one of those. 662 switch (MI.getOpcode()) { 663 case ARM::tBcc: 664 case ARM::t2Bcc: 665 case ARM::tCBZ: 666 case ARM::tCBNZ: 667 case ARM::tCPS: 668 case ARM::t2CPS3p: 669 case ARM::t2CPS2p: 670 case ARM::t2CPS1p: 671 case ARM::tMOVSr: 672 case ARM::tSETEND: 673 // Some instructions (mostly conditional branches) are not 674 // allowed in IT blocks. 675 if (ITBlock.instrInITBlock()) 676 S = SoftFail; 677 else 678 return Success; 679 break; 680 case ARM::tB: 681 case ARM::t2B: 682 case ARM::t2TBB: 683 case ARM::t2TBH: 684 // Some instructions (mostly unconditional branches) can 685 // only appears at the end of, or outside of, an IT. 686 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 687 S = SoftFail; 688 break; 689 default: 690 break; 691 } 692 693 // If we're in an IT block, base the predicate on that. Otherwise, 694 // assume a predicate of AL. 695 unsigned CC; 696 CC = ITBlock.getITCC(); 697 if (CC == 0xF) 698 CC = ARMCC::AL; 699 if (ITBlock.instrInITBlock()) 700 ITBlock.advanceITState(); 701 702 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 703 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 704 MCInst::iterator I = MI.begin(); 705 for (unsigned i = 0; i < NumOps; ++i, ++I) { 706 if (I == MI.end()) break; 707 if (OpInfo[i].isPredicate()) { 708 I = MI.insert(I, MCOperand::CreateImm(CC)); 709 ++I; 710 if (CC == ARMCC::AL) 711 MI.insert(I, MCOperand::CreateReg(0)); 712 else 713 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 714 return S; 715 } 716 } 717 718 I = MI.insert(I, MCOperand::CreateImm(CC)); 719 ++I; 720 if (CC == ARMCC::AL) 721 MI.insert(I, MCOperand::CreateReg(0)); 722 else 723 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 724 725 return S; 726 } 727 728 // Thumb VFP instructions are a special case. Because we share their 729 // encodings between ARM and Thumb modes, and they are predicable in ARM 730 // mode, the auto-generated decoder will give them an (incorrect) 731 // predicate operand. We need to rewrite these operands based on the IT 732 // context as a post-pass. 733 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 734 unsigned CC; 735 CC = ITBlock.getITCC(); 736 if (ITBlock.instrInITBlock()) 737 ITBlock.advanceITState(); 738 739 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 740 MCInst::iterator I = MI.begin(); 741 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 742 for (unsigned i = 0; i < NumOps; ++i, ++I) { 743 if (OpInfo[i].isPredicate() ) { 744 I->setImm(CC); 745 ++I; 746 if (CC == ARMCC::AL) 747 I->setReg(0); 748 else 749 I->setReg(ARM::CPSR); 750 return; 751 } 752 } 753 } 754 755 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 756 const MemoryObject &Region, 757 uint64_t Address, 758 raw_ostream &os, 759 raw_ostream &cs) const { 760 CommentStream = &cs; 761 762 uint8_t bytes[4]; 763 764 assert((STI.getFeatureBits() & ARM::ModeThumb) && 765 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 766 767 // We want to read exactly 2 bytes of data. 768 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 769 Size = 0; 770 return MCDisassembler::Fail; 771 } 772 773 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 774 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 775 Address, this, STI); 776 if (result != MCDisassembler::Fail) { 777 Size = 2; 778 Check(result, AddThumbPredicate(MI)); 779 return result; 780 } 781 782 MI.clear(); 783 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 784 Address, this, STI); 785 if (result) { 786 Size = 2; 787 bool InITBlock = ITBlock.instrInITBlock(); 788 Check(result, AddThumbPredicate(MI)); 789 AddThumb1SBit(MI, InITBlock); 790 return result; 791 } 792 793 MI.clear(); 794 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 795 Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 2; 798 799 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 800 // the Thumb predicate. 801 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 802 result = MCDisassembler::SoftFail; 803 804 Check(result, AddThumbPredicate(MI)); 805 806 // If we find an IT instruction, we need to parse its condition 807 // code and mask operands so that we can apply them correctly 808 // to the subsequent instructions. 809 if (MI.getOpcode() == ARM::t2IT) { 810 811 unsigned Firstcond = MI.getOperand(0).getImm(); 812 unsigned Mask = MI.getOperand(1).getImm(); 813 ITBlock.setITState(Firstcond, Mask); 814 } 815 816 return result; 817 } 818 819 // We want to read exactly 4 bytes of data. 820 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 821 Size = 0; 822 return MCDisassembler::Fail; 823 } 824 825 uint32_t insn32 = (bytes[3] << 8) | 826 (bytes[2] << 0) | 827 (bytes[1] << 24) | 828 (bytes[0] << 16); 829 MI.clear(); 830 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 831 this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 bool InITBlock = ITBlock.instrInITBlock(); 835 Check(result, AddThumbPredicate(MI)); 836 AddThumb1SBit(MI, InITBlock); 837 return result; 838 } 839 840 MI.clear(); 841 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 842 this, STI); 843 if (result != MCDisassembler::Fail) { 844 Size = 4; 845 Check(result, AddThumbPredicate(MI)); 846 return result; 847 } 848 849 MI.clear(); 850 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 851 if (result != MCDisassembler::Fail) { 852 Size = 4; 853 UpdateThumbVFPPredicate(MI); 854 return result; 855 } 856 857 MI.clear(); 858 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 859 this, STI); 860 if (result != MCDisassembler::Fail) { 861 Size = 4; 862 Check(result, AddThumbPredicate(MI)); 863 return result; 864 } 865 866 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 867 MI.clear(); 868 uint32_t NEONLdStInsn = insn32; 869 NEONLdStInsn &= 0xF0FFFFFF; 870 NEONLdStInsn |= 0x04000000; 871 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 872 Address, this, STI); 873 if (result != MCDisassembler::Fail) { 874 Size = 4; 875 Check(result, AddThumbPredicate(MI)); 876 return result; 877 } 878 } 879 880 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 881 MI.clear(); 882 uint32_t NEONDataInsn = insn32; 883 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 884 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 885 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 886 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 887 Address, this, STI); 888 if (result != MCDisassembler::Fail) { 889 Size = 4; 890 Check(result, AddThumbPredicate(MI)); 891 return result; 892 } 893 } 894 895 Size = 0; 896 return MCDisassembler::Fail; 897 } 898 899 900 extern "C" void LLVMInitializeARMDisassembler() { 901 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 902 createARMDisassembler); 903 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 904 createThumbDisassembler); 905 } 906 907 static const uint16_t GPRDecoderTable[] = { 908 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 909 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 910 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 911 ARM::R12, ARM::SP, ARM::LR, ARM::PC 912 }; 913 914 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) { 916 if (RegNo > 15) 917 return MCDisassembler::Fail; 918 919 unsigned Register = GPRDecoderTable[RegNo]; 920 Inst.addOperand(MCOperand::CreateReg(Register)); 921 return MCDisassembler::Success; 922 } 923 924 static DecodeStatus 925 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 926 uint64_t Address, const void *Decoder) { 927 DecodeStatus S = MCDisassembler::Success; 928 929 if (RegNo == 15) 930 S = MCDisassembler::SoftFail; 931 932 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 933 934 return S; 935 } 936 937 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 if (RegNo > 7) 940 return MCDisassembler::Fail; 941 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 942 } 943 944 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 945 uint64_t Address, const void *Decoder) { 946 unsigned Register = 0; 947 switch (RegNo) { 948 case 0: 949 Register = ARM::R0; 950 break; 951 case 1: 952 Register = ARM::R1; 953 break; 954 case 2: 955 Register = ARM::R2; 956 break; 957 case 3: 958 Register = ARM::R3; 959 break; 960 case 9: 961 Register = ARM::R9; 962 break; 963 case 12: 964 Register = ARM::R12; 965 break; 966 default: 967 return MCDisassembler::Fail; 968 } 969 970 Inst.addOperand(MCOperand::CreateReg(Register)); 971 return MCDisassembler::Success; 972 } 973 974 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 977 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 978 } 979 980 static const uint16_t SPRDecoderTable[] = { 981 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 982 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 983 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 984 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 985 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 986 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 987 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 988 ARM::S28, ARM::S29, ARM::S30, ARM::S31 989 }; 990 991 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31) 994 return MCDisassembler::Fail; 995 996 unsigned Register = SPRDecoderTable[RegNo]; 997 Inst.addOperand(MCOperand::CreateReg(Register)); 998 return MCDisassembler::Success; 999 } 1000 1001 static const uint16_t DPRDecoderTable[] = { 1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1010 }; 1011 1012 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 if (RegNo > 31) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Register = DPRDecoderTable[RegNo]; 1018 Inst.addOperand(MCOperand::CreateReg(Register)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 if (RegNo > 7) 1025 return MCDisassembler::Fail; 1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1027 } 1028 1029 static DecodeStatus 1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 if (RegNo > 15) 1033 return MCDisassembler::Fail; 1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1035 } 1036 1037 static const uint16_t QPRDecoderTable[] = { 1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1042 }; 1043 1044 1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 31) 1048 return MCDisassembler::Fail; 1049 RegNo >>= 1; 1050 1051 unsigned Register = QPRDecoderTable[RegNo]; 1052 Inst.addOperand(MCOperand::CreateReg(Register)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static const uint16_t DPairDecoderTable[] = { 1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1062 ARM::Q15 1063 }; 1064 1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1066 uint64_t Address, const void *Decoder) { 1067 if (RegNo > 30) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Register = DPairDecoderTable[RegNo]; 1071 Inst.addOperand(MCOperand::CreateReg(Register)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static const uint16_t DPairSpacedDecoderTable[] = { 1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1083 ARM::D28_D30, ARM::D29_D31 1084 }; 1085 1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 29) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1094 Inst.addOperand(MCOperand::CreateReg(Register)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val == 0xF) return MCDisassembler::Fail; 1101 // AL predicate is not allowed on Thumb1 branches. 1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1103 return MCDisassembler::Fail; 1104 Inst.addOperand(MCOperand::CreateImm(Val)); 1105 if (Val == ARMCC::AL) { 1106 Inst.addOperand(MCOperand::CreateReg(0)); 1107 } else 1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 if (Val) 1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1116 else 1117 Inst.addOperand(MCOperand::CreateReg(0)); 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1122 uint64_t Address, const void *Decoder) { 1123 uint32_t imm = Val & 0xFF; 1124 uint32_t rot = (Val & 0xF00) >> 7; 1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1126 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1127 return MCDisassembler::Success; 1128 } 1129 1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1131 uint64_t Address, const void *Decoder) { 1132 DecodeStatus S = MCDisassembler::Success; 1133 1134 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1135 unsigned type = fieldFromInstruction(Val, 5, 2); 1136 unsigned imm = fieldFromInstruction(Val, 7, 5); 1137 1138 // Register-immediate 1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1140 return MCDisassembler::Fail; 1141 1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1143 switch (type) { 1144 case 0: 1145 Shift = ARM_AM::lsl; 1146 break; 1147 case 1: 1148 Shift = ARM_AM::lsr; 1149 break; 1150 case 2: 1151 Shift = ARM_AM::asr; 1152 break; 1153 case 3: 1154 Shift = ARM_AM::ror; 1155 break; 1156 } 1157 1158 if (Shift == ARM_AM::ror && imm == 0) 1159 Shift = ARM_AM::rrx; 1160 1161 unsigned Op = Shift | (imm << 3); 1162 Inst.addOperand(MCOperand::CreateImm(Op)); 1163 1164 return S; 1165 } 1166 1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1168 uint64_t Address, const void *Decoder) { 1169 DecodeStatus S = MCDisassembler::Success; 1170 1171 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1172 unsigned type = fieldFromInstruction(Val, 5, 2); 1173 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1174 1175 // Register-register 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1179 return MCDisassembler::Fail; 1180 1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1182 switch (type) { 1183 case 0: 1184 Shift = ARM_AM::lsl; 1185 break; 1186 case 1: 1187 Shift = ARM_AM::lsr; 1188 break; 1189 case 2: 1190 Shift = ARM_AM::asr; 1191 break; 1192 case 3: 1193 Shift = ARM_AM::ror; 1194 break; 1195 } 1196 1197 Inst.addOperand(MCOperand::CreateImm(Shift)); 1198 1199 return S; 1200 } 1201 1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1203 uint64_t Address, const void *Decoder) { 1204 DecodeStatus S = MCDisassembler::Success; 1205 1206 bool writebackLoad = false; 1207 unsigned writebackReg = 0; 1208 switch (Inst.getOpcode()) { 1209 default: 1210 break; 1211 case ARM::LDMIA_UPD: 1212 case ARM::LDMDB_UPD: 1213 case ARM::LDMIB_UPD: 1214 case ARM::LDMDA_UPD: 1215 case ARM::t2LDMIA_UPD: 1216 case ARM::t2LDMDB_UPD: 1217 writebackLoad = true; 1218 writebackReg = Inst.getOperand(0).getReg(); 1219 break; 1220 } 1221 1222 // Empty register lists are not allowed. 1223 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1224 for (unsigned i = 0; i < 16; ++i) { 1225 if (Val & (1 << i)) { 1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1227 return MCDisassembler::Fail; 1228 // Writeback not allowed if Rn is in the target list. 1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1230 Check(S, MCDisassembler::SoftFail); 1231 } 1232 } 1233 1234 return S; 1235 } 1236 1237 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1238 uint64_t Address, const void *Decoder) { 1239 DecodeStatus S = MCDisassembler::Success; 1240 1241 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1242 unsigned regs = fieldFromInstruction(Val, 0, 8); 1243 1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1245 return MCDisassembler::Fail; 1246 for (unsigned i = 0; i < (regs - 1); ++i) { 1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1248 return MCDisassembler::Fail; 1249 } 1250 1251 return S; 1252 } 1253 1254 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1255 uint64_t Address, const void *Decoder) { 1256 DecodeStatus S = MCDisassembler::Success; 1257 1258 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1259 unsigned regs = fieldFromInstruction(Val, 0, 8); 1260 1261 regs = regs >> 1; 1262 1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1264 return MCDisassembler::Fail; 1265 for (unsigned i = 0; i < (regs - 1); ++i) { 1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1267 return MCDisassembler::Fail; 1268 } 1269 1270 return S; 1271 } 1272 1273 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1274 uint64_t Address, const void *Decoder) { 1275 // This operand encodes a mask of contiguous zeros between a specified MSB 1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1277 // the mask of all bits LSB-and-lower, and then xor them to create 1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1279 // create the final mask. 1280 unsigned msb = fieldFromInstruction(Val, 5, 5); 1281 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1282 1283 DecodeStatus S = MCDisassembler::Success; 1284 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1285 1286 uint32_t msb_mask = 0xFFFFFFFF; 1287 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1288 uint32_t lsb_mask = (1U << lsb) - 1; 1289 1290 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1291 return S; 1292 } 1293 1294 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1295 uint64_t Address, const void *Decoder) { 1296 DecodeStatus S = MCDisassembler::Success; 1297 1298 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1299 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1300 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1301 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1302 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1303 unsigned U = fieldFromInstruction(Insn, 23, 1); 1304 1305 switch (Inst.getOpcode()) { 1306 case ARM::LDC_OFFSET: 1307 case ARM::LDC_PRE: 1308 case ARM::LDC_POST: 1309 case ARM::LDC_OPTION: 1310 case ARM::LDCL_OFFSET: 1311 case ARM::LDCL_PRE: 1312 case ARM::LDCL_POST: 1313 case ARM::LDCL_OPTION: 1314 case ARM::STC_OFFSET: 1315 case ARM::STC_PRE: 1316 case ARM::STC_POST: 1317 case ARM::STC_OPTION: 1318 case ARM::STCL_OFFSET: 1319 case ARM::STCL_PRE: 1320 case ARM::STCL_POST: 1321 case ARM::STCL_OPTION: 1322 case ARM::t2LDC_OFFSET: 1323 case ARM::t2LDC_PRE: 1324 case ARM::t2LDC_POST: 1325 case ARM::t2LDC_OPTION: 1326 case ARM::t2LDCL_OFFSET: 1327 case ARM::t2LDCL_PRE: 1328 case ARM::t2LDCL_POST: 1329 case ARM::t2LDCL_OPTION: 1330 case ARM::t2STC_OFFSET: 1331 case ARM::t2STC_PRE: 1332 case ARM::t2STC_POST: 1333 case ARM::t2STC_OPTION: 1334 case ARM::t2STCL_OFFSET: 1335 case ARM::t2STCL_PRE: 1336 case ARM::t2STCL_POST: 1337 case ARM::t2STCL_OPTION: 1338 if (coproc == 0xA || coproc == 0xB) 1339 return MCDisassembler::Fail; 1340 break; 1341 default: 1342 break; 1343 } 1344 1345 Inst.addOperand(MCOperand::CreateImm(coproc)); 1346 Inst.addOperand(MCOperand::CreateImm(CRd)); 1347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1348 return MCDisassembler::Fail; 1349 1350 switch (Inst.getOpcode()) { 1351 case ARM::t2LDC2_OFFSET: 1352 case ARM::t2LDC2L_OFFSET: 1353 case ARM::t2LDC2_PRE: 1354 case ARM::t2LDC2L_PRE: 1355 case ARM::t2STC2_OFFSET: 1356 case ARM::t2STC2L_OFFSET: 1357 case ARM::t2STC2_PRE: 1358 case ARM::t2STC2L_PRE: 1359 case ARM::LDC2_OFFSET: 1360 case ARM::LDC2L_OFFSET: 1361 case ARM::LDC2_PRE: 1362 case ARM::LDC2L_PRE: 1363 case ARM::STC2_OFFSET: 1364 case ARM::STC2L_OFFSET: 1365 case ARM::STC2_PRE: 1366 case ARM::STC2L_PRE: 1367 case ARM::t2LDC_OFFSET: 1368 case ARM::t2LDCL_OFFSET: 1369 case ARM::t2LDC_PRE: 1370 case ARM::t2LDCL_PRE: 1371 case ARM::t2STC_OFFSET: 1372 case ARM::t2STCL_OFFSET: 1373 case ARM::t2STC_PRE: 1374 case ARM::t2STCL_PRE: 1375 case ARM::LDC_OFFSET: 1376 case ARM::LDCL_OFFSET: 1377 case ARM::LDC_PRE: 1378 case ARM::LDCL_PRE: 1379 case ARM::STC_OFFSET: 1380 case ARM::STCL_OFFSET: 1381 case ARM::STC_PRE: 1382 case ARM::STCL_PRE: 1383 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1384 Inst.addOperand(MCOperand::CreateImm(imm)); 1385 break; 1386 case ARM::t2LDC2_POST: 1387 case ARM::t2LDC2L_POST: 1388 case ARM::t2STC2_POST: 1389 case ARM::t2STC2L_POST: 1390 case ARM::LDC2_POST: 1391 case ARM::LDC2L_POST: 1392 case ARM::STC2_POST: 1393 case ARM::STC2L_POST: 1394 case ARM::t2LDC_POST: 1395 case ARM::t2LDCL_POST: 1396 case ARM::t2STC_POST: 1397 case ARM::t2STCL_POST: 1398 case ARM::LDC_POST: 1399 case ARM::LDCL_POST: 1400 case ARM::STC_POST: 1401 case ARM::STCL_POST: 1402 imm |= U << 8; 1403 // fall through. 1404 default: 1405 // The 'option' variant doesn't encode 'U' in the immediate since 1406 // the immediate is unsigned [0,255]. 1407 Inst.addOperand(MCOperand::CreateImm(imm)); 1408 break; 1409 } 1410 1411 switch (Inst.getOpcode()) { 1412 case ARM::LDC_OFFSET: 1413 case ARM::LDC_PRE: 1414 case ARM::LDC_POST: 1415 case ARM::LDC_OPTION: 1416 case ARM::LDCL_OFFSET: 1417 case ARM::LDCL_PRE: 1418 case ARM::LDCL_POST: 1419 case ARM::LDCL_OPTION: 1420 case ARM::STC_OFFSET: 1421 case ARM::STC_PRE: 1422 case ARM::STC_POST: 1423 case ARM::STC_OPTION: 1424 case ARM::STCL_OFFSET: 1425 case ARM::STCL_PRE: 1426 case ARM::STCL_POST: 1427 case ARM::STCL_OPTION: 1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1429 return MCDisassembler::Fail; 1430 break; 1431 default: 1432 break; 1433 } 1434 1435 return S; 1436 } 1437 1438 static DecodeStatus 1439 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1440 uint64_t Address, const void *Decoder) { 1441 DecodeStatus S = MCDisassembler::Success; 1442 1443 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1444 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1445 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1446 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1447 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1448 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1449 unsigned P = fieldFromInstruction(Insn, 24, 1); 1450 unsigned W = fieldFromInstruction(Insn, 21, 1); 1451 1452 // On stores, the writeback operand precedes Rt. 1453 switch (Inst.getOpcode()) { 1454 case ARM::STR_POST_IMM: 1455 case ARM::STR_POST_REG: 1456 case ARM::STRB_POST_IMM: 1457 case ARM::STRB_POST_REG: 1458 case ARM::STRT_POST_REG: 1459 case ARM::STRT_POST_IMM: 1460 case ARM::STRBT_POST_REG: 1461 case ARM::STRBT_POST_IMM: 1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1463 return MCDisassembler::Fail; 1464 break; 1465 default: 1466 break; 1467 } 1468 1469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1470 return MCDisassembler::Fail; 1471 1472 // On loads, the writeback operand comes after Rt. 1473 switch (Inst.getOpcode()) { 1474 case ARM::LDR_POST_IMM: 1475 case ARM::LDR_POST_REG: 1476 case ARM::LDRB_POST_IMM: 1477 case ARM::LDRB_POST_REG: 1478 case ARM::LDRBT_POST_REG: 1479 case ARM::LDRBT_POST_IMM: 1480 case ARM::LDRT_POST_REG: 1481 case ARM::LDRT_POST_IMM: 1482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1483 return MCDisassembler::Fail; 1484 break; 1485 default: 1486 break; 1487 } 1488 1489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1490 return MCDisassembler::Fail; 1491 1492 ARM_AM::AddrOpc Op = ARM_AM::add; 1493 if (!fieldFromInstruction(Insn, 23, 1)) 1494 Op = ARM_AM::sub; 1495 1496 bool writeback = (P == 0) || (W == 1); 1497 unsigned idx_mode = 0; 1498 if (P && writeback) 1499 idx_mode = ARMII::IndexModePre; 1500 else if (!P && writeback) 1501 idx_mode = ARMII::IndexModePost; 1502 1503 if (writeback && (Rn == 15 || Rn == Rt)) 1504 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1505 1506 if (reg) { 1507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1510 switch( fieldFromInstruction(Insn, 5, 2)) { 1511 case 0: 1512 Opc = ARM_AM::lsl; 1513 break; 1514 case 1: 1515 Opc = ARM_AM::lsr; 1516 break; 1517 case 2: 1518 Opc = ARM_AM::asr; 1519 break; 1520 case 3: 1521 Opc = ARM_AM::ror; 1522 break; 1523 default: 1524 return MCDisassembler::Fail; 1525 } 1526 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1527 if (Opc == ARM_AM::ror && amt == 0) 1528 Opc = ARM_AM::rrx; 1529 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1530 1531 Inst.addOperand(MCOperand::CreateImm(imm)); 1532 } else { 1533 Inst.addOperand(MCOperand::CreateReg(0)); 1534 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1535 Inst.addOperand(MCOperand::CreateImm(tmp)); 1536 } 1537 1538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1539 return MCDisassembler::Fail; 1540 1541 return S; 1542 } 1543 1544 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1545 uint64_t Address, const void *Decoder) { 1546 DecodeStatus S = MCDisassembler::Success; 1547 1548 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1549 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1550 unsigned type = fieldFromInstruction(Val, 5, 2); 1551 unsigned imm = fieldFromInstruction(Val, 7, 5); 1552 unsigned U = fieldFromInstruction(Val, 12, 1); 1553 1554 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1555 switch (type) { 1556 case 0: 1557 ShOp = ARM_AM::lsl; 1558 break; 1559 case 1: 1560 ShOp = ARM_AM::lsr; 1561 break; 1562 case 2: 1563 ShOp = ARM_AM::asr; 1564 break; 1565 case 3: 1566 ShOp = ARM_AM::ror; 1567 break; 1568 } 1569 1570 if (ShOp == ARM_AM::ror && imm == 0) 1571 ShOp = ARM_AM::rrx; 1572 1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1574 return MCDisassembler::Fail; 1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 unsigned shift; 1578 if (U) 1579 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1580 else 1581 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1582 Inst.addOperand(MCOperand::CreateImm(shift)); 1583 1584 return S; 1585 } 1586 1587 static DecodeStatus 1588 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1589 uint64_t Address, const void *Decoder) { 1590 DecodeStatus S = MCDisassembler::Success; 1591 1592 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1593 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1594 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1595 unsigned type = fieldFromInstruction(Insn, 22, 1); 1596 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1597 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1598 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1599 unsigned W = fieldFromInstruction(Insn, 21, 1); 1600 unsigned P = fieldFromInstruction(Insn, 24, 1); 1601 unsigned Rt2 = Rt + 1; 1602 1603 bool writeback = (W == 1) | (P == 0); 1604 1605 // For {LD,ST}RD, Rt must be even, else undefined. 1606 switch (Inst.getOpcode()) { 1607 case ARM::STRD: 1608 case ARM::STRD_PRE: 1609 case ARM::STRD_POST: 1610 case ARM::LDRD: 1611 case ARM::LDRD_PRE: 1612 case ARM::LDRD_POST: 1613 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1614 break; 1615 default: 1616 break; 1617 } 1618 switch (Inst.getOpcode()) { 1619 case ARM::STRD: 1620 case ARM::STRD_PRE: 1621 case ARM::STRD_POST: 1622 if (P == 0 && W == 1) 1623 S = MCDisassembler::SoftFail; 1624 1625 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1626 S = MCDisassembler::SoftFail; 1627 if (type && Rm == 15) 1628 S = MCDisassembler::SoftFail; 1629 if (Rt2 == 15) 1630 S = MCDisassembler::SoftFail; 1631 if (!type && fieldFromInstruction(Insn, 8, 4)) 1632 S = MCDisassembler::SoftFail; 1633 break; 1634 case ARM::STRH: 1635 case ARM::STRH_PRE: 1636 case ARM::STRH_POST: 1637 if (Rt == 15) 1638 S = MCDisassembler::SoftFail; 1639 if (writeback && (Rn == 15 || Rn == Rt)) 1640 S = MCDisassembler::SoftFail; 1641 if (!type && Rm == 15) 1642 S = MCDisassembler::SoftFail; 1643 break; 1644 case ARM::LDRD: 1645 case ARM::LDRD_PRE: 1646 case ARM::LDRD_POST: 1647 if (type && Rn == 15){ 1648 if (Rt2 == 15) 1649 S = MCDisassembler::SoftFail; 1650 break; 1651 } 1652 if (P == 0 && W == 1) 1653 S = MCDisassembler::SoftFail; 1654 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1655 S = MCDisassembler::SoftFail; 1656 if (!type && writeback && Rn == 15) 1657 S = MCDisassembler::SoftFail; 1658 if (writeback && (Rn == Rt || Rn == Rt2)) 1659 S = MCDisassembler::SoftFail; 1660 break; 1661 case ARM::LDRH: 1662 case ARM::LDRH_PRE: 1663 case ARM::LDRH_POST: 1664 if (type && Rn == 15){ 1665 if (Rt == 15) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 } 1669 if (Rt == 15) 1670 S = MCDisassembler::SoftFail; 1671 if (!type && Rm == 15) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1674 S = MCDisassembler::SoftFail; 1675 break; 1676 case ARM::LDRSH: 1677 case ARM::LDRSH_PRE: 1678 case ARM::LDRSH_POST: 1679 case ARM::LDRSB: 1680 case ARM::LDRSB_PRE: 1681 case ARM::LDRSB_POST: 1682 if (type && Rn == 15){ 1683 if (Rt == 15) 1684 S = MCDisassembler::SoftFail; 1685 break; 1686 } 1687 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1688 S = MCDisassembler::SoftFail; 1689 if (!type && (Rt == 15 || Rm == 15)) 1690 S = MCDisassembler::SoftFail; 1691 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1692 S = MCDisassembler::SoftFail; 1693 break; 1694 default: 1695 break; 1696 } 1697 1698 if (writeback) { // Writeback 1699 if (P) 1700 U |= ARMII::IndexModePre << 9; 1701 else 1702 U |= ARMII::IndexModePost << 9; 1703 1704 // On stores, the writeback operand precedes Rt. 1705 switch (Inst.getOpcode()) { 1706 case ARM::STRD: 1707 case ARM::STRD_PRE: 1708 case ARM::STRD_POST: 1709 case ARM::STRH: 1710 case ARM::STRH_PRE: 1711 case ARM::STRH_POST: 1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 break; 1715 default: 1716 break; 1717 } 1718 } 1719 1720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1721 return MCDisassembler::Fail; 1722 switch (Inst.getOpcode()) { 1723 case ARM::STRD: 1724 case ARM::STRD_PRE: 1725 case ARM::STRD_POST: 1726 case ARM::LDRD: 1727 case ARM::LDRD_PRE: 1728 case ARM::LDRD_POST: 1729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1730 return MCDisassembler::Fail; 1731 break; 1732 default: 1733 break; 1734 } 1735 1736 if (writeback) { 1737 // On loads, the writeback operand comes after Rt. 1738 switch (Inst.getOpcode()) { 1739 case ARM::LDRD: 1740 case ARM::LDRD_PRE: 1741 case ARM::LDRD_POST: 1742 case ARM::LDRH: 1743 case ARM::LDRH_PRE: 1744 case ARM::LDRH_POST: 1745 case ARM::LDRSH: 1746 case ARM::LDRSH_PRE: 1747 case ARM::LDRSH_POST: 1748 case ARM::LDRSB: 1749 case ARM::LDRSB_PRE: 1750 case ARM::LDRSB_POST: 1751 case ARM::LDRHTr: 1752 case ARM::LDRSBTr: 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 break; 1756 default: 1757 break; 1758 } 1759 } 1760 1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1762 return MCDisassembler::Fail; 1763 1764 if (type) { 1765 Inst.addOperand(MCOperand::CreateReg(0)); 1766 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1767 } else { 1768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1769 return MCDisassembler::Fail; 1770 Inst.addOperand(MCOperand::CreateImm(U)); 1771 } 1772 1773 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1774 return MCDisassembler::Fail; 1775 1776 return S; 1777 } 1778 1779 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1780 uint64_t Address, const void *Decoder) { 1781 DecodeStatus S = MCDisassembler::Success; 1782 1783 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1784 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1785 1786 switch (mode) { 1787 case 0: 1788 mode = ARM_AM::da; 1789 break; 1790 case 1: 1791 mode = ARM_AM::ia; 1792 break; 1793 case 2: 1794 mode = ARM_AM::db; 1795 break; 1796 case 3: 1797 mode = ARM_AM::ib; 1798 break; 1799 } 1800 1801 Inst.addOperand(MCOperand::CreateImm(mode)); 1802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1803 return MCDisassembler::Fail; 1804 1805 return S; 1806 } 1807 1808 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1809 unsigned Insn, 1810 uint64_t Address, const void *Decoder) { 1811 DecodeStatus S = MCDisassembler::Success; 1812 1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1814 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1815 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1816 1817 if (pred == 0xF) { 1818 switch (Inst.getOpcode()) { 1819 case ARM::LDMDA: 1820 Inst.setOpcode(ARM::RFEDA); 1821 break; 1822 case ARM::LDMDA_UPD: 1823 Inst.setOpcode(ARM::RFEDA_UPD); 1824 break; 1825 case ARM::LDMDB: 1826 Inst.setOpcode(ARM::RFEDB); 1827 break; 1828 case ARM::LDMDB_UPD: 1829 Inst.setOpcode(ARM::RFEDB_UPD); 1830 break; 1831 case ARM::LDMIA: 1832 Inst.setOpcode(ARM::RFEIA); 1833 break; 1834 case ARM::LDMIA_UPD: 1835 Inst.setOpcode(ARM::RFEIA_UPD); 1836 break; 1837 case ARM::LDMIB: 1838 Inst.setOpcode(ARM::RFEIB); 1839 break; 1840 case ARM::LDMIB_UPD: 1841 Inst.setOpcode(ARM::RFEIB_UPD); 1842 break; 1843 case ARM::STMDA: 1844 Inst.setOpcode(ARM::SRSDA); 1845 break; 1846 case ARM::STMDA_UPD: 1847 Inst.setOpcode(ARM::SRSDA_UPD); 1848 break; 1849 case ARM::STMDB: 1850 Inst.setOpcode(ARM::SRSDB); 1851 break; 1852 case ARM::STMDB_UPD: 1853 Inst.setOpcode(ARM::SRSDB_UPD); 1854 break; 1855 case ARM::STMIA: 1856 Inst.setOpcode(ARM::SRSIA); 1857 break; 1858 case ARM::STMIA_UPD: 1859 Inst.setOpcode(ARM::SRSIA_UPD); 1860 break; 1861 case ARM::STMIB: 1862 Inst.setOpcode(ARM::SRSIB); 1863 break; 1864 case ARM::STMIB_UPD: 1865 Inst.setOpcode(ARM::SRSIB_UPD); 1866 break; 1867 default: 1868 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1869 } 1870 1871 // For stores (which become SRS's, the only operand is the mode. 1872 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1873 Inst.addOperand( 1874 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1875 return S; 1876 } 1877 1878 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1879 } 1880 1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1884 return MCDisassembler::Fail; // Tied 1885 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1886 return MCDisassembler::Fail; 1887 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 1890 return S; 1891 } 1892 1893 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1894 uint64_t Address, const void *Decoder) { 1895 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1896 unsigned M = fieldFromInstruction(Insn, 17, 1); 1897 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1898 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1899 1900 DecodeStatus S = MCDisassembler::Success; 1901 1902 // imod == '01' --> UNPREDICTABLE 1903 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1904 // return failure here. The '01' imod value is unprintable, so there's 1905 // nothing useful we could do even if we returned UNPREDICTABLE. 1906 1907 if (imod == 1) return MCDisassembler::Fail; 1908 1909 if (imod && M) { 1910 Inst.setOpcode(ARM::CPS3p); 1911 Inst.addOperand(MCOperand::CreateImm(imod)); 1912 Inst.addOperand(MCOperand::CreateImm(iflags)); 1913 Inst.addOperand(MCOperand::CreateImm(mode)); 1914 } else if (imod && !M) { 1915 Inst.setOpcode(ARM::CPS2p); 1916 Inst.addOperand(MCOperand::CreateImm(imod)); 1917 Inst.addOperand(MCOperand::CreateImm(iflags)); 1918 if (mode) S = MCDisassembler::SoftFail; 1919 } else if (!imod && M) { 1920 Inst.setOpcode(ARM::CPS1p); 1921 Inst.addOperand(MCOperand::CreateImm(mode)); 1922 if (iflags) S = MCDisassembler::SoftFail; 1923 } else { 1924 // imod == '00' && M == '0' --> UNPREDICTABLE 1925 Inst.setOpcode(ARM::CPS1p); 1926 Inst.addOperand(MCOperand::CreateImm(mode)); 1927 S = MCDisassembler::SoftFail; 1928 } 1929 1930 return S; 1931 } 1932 1933 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1934 uint64_t Address, const void *Decoder) { 1935 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1936 unsigned M = fieldFromInstruction(Insn, 8, 1); 1937 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1938 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1939 1940 DecodeStatus S = MCDisassembler::Success; 1941 1942 // imod == '01' --> UNPREDICTABLE 1943 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1944 // return failure here. The '01' imod value is unprintable, so there's 1945 // nothing useful we could do even if we returned UNPREDICTABLE. 1946 1947 if (imod == 1) return MCDisassembler::Fail; 1948 1949 if (imod && M) { 1950 Inst.setOpcode(ARM::t2CPS3p); 1951 Inst.addOperand(MCOperand::CreateImm(imod)); 1952 Inst.addOperand(MCOperand::CreateImm(iflags)); 1953 Inst.addOperand(MCOperand::CreateImm(mode)); 1954 } else if (imod && !M) { 1955 Inst.setOpcode(ARM::t2CPS2p); 1956 Inst.addOperand(MCOperand::CreateImm(imod)); 1957 Inst.addOperand(MCOperand::CreateImm(iflags)); 1958 if (mode) S = MCDisassembler::SoftFail; 1959 } else if (!imod && M) { 1960 Inst.setOpcode(ARM::t2CPS1p); 1961 Inst.addOperand(MCOperand::CreateImm(mode)); 1962 if (iflags) S = MCDisassembler::SoftFail; 1963 } else { 1964 // imod == '00' && M == '0' --> UNPREDICTABLE 1965 Inst.setOpcode(ARM::t2CPS1p); 1966 Inst.addOperand(MCOperand::CreateImm(mode)); 1967 S = MCDisassembler::SoftFail; 1968 } 1969 1970 return S; 1971 } 1972 1973 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 DecodeStatus S = MCDisassembler::Success; 1976 1977 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1978 unsigned imm = 0; 1979 1980 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1981 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1982 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1983 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1984 1985 if (Inst.getOpcode() == ARM::t2MOVTi16) 1986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1987 return MCDisassembler::Fail; 1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 1991 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1992 Inst.addOperand(MCOperand::CreateImm(imm)); 1993 1994 return S; 1995 } 1996 1997 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1998 uint64_t Address, const void *Decoder) { 1999 DecodeStatus S = MCDisassembler::Success; 2000 2001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2002 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2003 unsigned imm = 0; 2004 2005 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2006 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2007 2008 if (Inst.getOpcode() == ARM::MOVTi16) 2009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2012 return MCDisassembler::Fail; 2013 2014 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2015 Inst.addOperand(MCOperand::CreateImm(imm)); 2016 2017 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 2020 return S; 2021 } 2022 2023 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2024 uint64_t Address, const void *Decoder) { 2025 DecodeStatus S = MCDisassembler::Success; 2026 2027 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2028 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2029 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2030 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2031 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2032 2033 if (pred == 0xF) 2034 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2035 2036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2037 return MCDisassembler::Fail; 2038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2041 return MCDisassembler::Fail; 2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2043 return MCDisassembler::Fail; 2044 2045 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 2048 return S; 2049 } 2050 2051 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2052 uint64_t Address, const void *Decoder) { 2053 DecodeStatus S = MCDisassembler::Success; 2054 2055 unsigned add = fieldFromInstruction(Val, 12, 1); 2056 unsigned imm = fieldFromInstruction(Val, 0, 12); 2057 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2058 2059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2060 return MCDisassembler::Fail; 2061 2062 if (!add) imm *= -1; 2063 if (imm == 0 && !add) imm = INT32_MIN; 2064 Inst.addOperand(MCOperand::CreateImm(imm)); 2065 if (Rn == 15) 2066 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2067 2068 return S; 2069 } 2070 2071 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2072 uint64_t Address, const void *Decoder) { 2073 DecodeStatus S = MCDisassembler::Success; 2074 2075 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2076 unsigned U = fieldFromInstruction(Val, 8, 1); 2077 unsigned imm = fieldFromInstruction(Val, 0, 8); 2078 2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 2082 if (U) 2083 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2084 else 2085 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2086 2087 return S; 2088 } 2089 2090 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2091 uint64_t Address, const void *Decoder) { 2092 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2093 } 2094 2095 static DecodeStatus 2096 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2097 uint64_t Address, const void *Decoder) { 2098 DecodeStatus Status = MCDisassembler::Success; 2099 2100 // Note the J1 and J2 values are from the encoded instruction. So here 2101 // change them to I1 and I2 values via as documented: 2102 // I1 = NOT(J1 EOR S); 2103 // I2 = NOT(J2 EOR S); 2104 // and build the imm32 with one trailing zero as documented: 2105 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2106 unsigned S = fieldFromInstruction(Insn, 26, 1); 2107 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2108 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2109 unsigned I1 = !(J1 ^ S); 2110 unsigned I2 = !(J2 ^ S); 2111 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2112 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2113 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2114 int imm32 = SignExtend32<24>(tmp << 1); 2115 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2116 true, 4, Inst, Decoder)) 2117 Inst.addOperand(MCOperand::CreateImm(imm32)); 2118 2119 return Status; 2120 } 2121 2122 static DecodeStatus 2123 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2124 uint64_t Address, const void *Decoder) { 2125 DecodeStatus S = MCDisassembler::Success; 2126 2127 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2128 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2129 2130 if (pred == 0xF) { 2131 Inst.setOpcode(ARM::BLXi); 2132 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2133 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2134 true, 4, Inst, Decoder)) 2135 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2136 return S; 2137 } 2138 2139 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2140 true, 4, Inst, Decoder)) 2141 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2142 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2143 return MCDisassembler::Fail; 2144 2145 return S; 2146 } 2147 2148 2149 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2150 uint64_t Address, const void *Decoder) { 2151 DecodeStatus S = MCDisassembler::Success; 2152 2153 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2154 unsigned align = fieldFromInstruction(Val, 4, 2); 2155 2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 if (!align) 2159 Inst.addOperand(MCOperand::CreateImm(0)); 2160 else 2161 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2162 2163 return S; 2164 } 2165 2166 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2167 uint64_t Address, const void *Decoder) { 2168 DecodeStatus S = MCDisassembler::Success; 2169 2170 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2172 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2173 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2174 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2175 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2176 2177 // First output register 2178 switch (Inst.getOpcode()) { 2179 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2180 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2181 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2182 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2183 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2184 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2185 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2186 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2187 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2188 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2189 return MCDisassembler::Fail; 2190 break; 2191 case ARM::VLD2b16: 2192 case ARM::VLD2b32: 2193 case ARM::VLD2b8: 2194 case ARM::VLD2b16wb_fixed: 2195 case ARM::VLD2b16wb_register: 2196 case ARM::VLD2b32wb_fixed: 2197 case ARM::VLD2b32wb_register: 2198 case ARM::VLD2b8wb_fixed: 2199 case ARM::VLD2b8wb_register: 2200 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 break; 2203 default: 2204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 } 2207 2208 // Second output register 2209 switch (Inst.getOpcode()) { 2210 case ARM::VLD3d8: 2211 case ARM::VLD3d16: 2212 case ARM::VLD3d32: 2213 case ARM::VLD3d8_UPD: 2214 case ARM::VLD3d16_UPD: 2215 case ARM::VLD3d32_UPD: 2216 case ARM::VLD4d8: 2217 case ARM::VLD4d16: 2218 case ARM::VLD4d32: 2219 case ARM::VLD4d8_UPD: 2220 case ARM::VLD4d16_UPD: 2221 case ARM::VLD4d32_UPD: 2222 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2223 return MCDisassembler::Fail; 2224 break; 2225 case ARM::VLD3q8: 2226 case ARM::VLD3q16: 2227 case ARM::VLD3q32: 2228 case ARM::VLD3q8_UPD: 2229 case ARM::VLD3q16_UPD: 2230 case ARM::VLD3q32_UPD: 2231 case ARM::VLD4q8: 2232 case ARM::VLD4q16: 2233 case ARM::VLD4q32: 2234 case ARM::VLD4q8_UPD: 2235 case ARM::VLD4q16_UPD: 2236 case ARM::VLD4q32_UPD: 2237 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2238 return MCDisassembler::Fail; 2239 default: 2240 break; 2241 } 2242 2243 // Third output register 2244 switch(Inst.getOpcode()) { 2245 case ARM::VLD3d8: 2246 case ARM::VLD3d16: 2247 case ARM::VLD3d32: 2248 case ARM::VLD3d8_UPD: 2249 case ARM::VLD3d16_UPD: 2250 case ARM::VLD3d32_UPD: 2251 case ARM::VLD4d8: 2252 case ARM::VLD4d16: 2253 case ARM::VLD4d32: 2254 case ARM::VLD4d8_UPD: 2255 case ARM::VLD4d16_UPD: 2256 case ARM::VLD4d32_UPD: 2257 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2258 return MCDisassembler::Fail; 2259 break; 2260 case ARM::VLD3q8: 2261 case ARM::VLD3q16: 2262 case ARM::VLD3q32: 2263 case ARM::VLD3q8_UPD: 2264 case ARM::VLD3q16_UPD: 2265 case ARM::VLD3q32_UPD: 2266 case ARM::VLD4q8: 2267 case ARM::VLD4q16: 2268 case ARM::VLD4q32: 2269 case ARM::VLD4q8_UPD: 2270 case ARM::VLD4q16_UPD: 2271 case ARM::VLD4q32_UPD: 2272 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2273 return MCDisassembler::Fail; 2274 break; 2275 default: 2276 break; 2277 } 2278 2279 // Fourth output register 2280 switch (Inst.getOpcode()) { 2281 case ARM::VLD4d8: 2282 case ARM::VLD4d16: 2283 case ARM::VLD4d32: 2284 case ARM::VLD4d8_UPD: 2285 case ARM::VLD4d16_UPD: 2286 case ARM::VLD4d32_UPD: 2287 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 break; 2290 case ARM::VLD4q8: 2291 case ARM::VLD4q16: 2292 case ARM::VLD4q32: 2293 case ARM::VLD4q8_UPD: 2294 case ARM::VLD4q16_UPD: 2295 case ARM::VLD4q32_UPD: 2296 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2297 return MCDisassembler::Fail; 2298 break; 2299 default: 2300 break; 2301 } 2302 2303 // Writeback operand 2304 switch (Inst.getOpcode()) { 2305 case ARM::VLD1d8wb_fixed: 2306 case ARM::VLD1d16wb_fixed: 2307 case ARM::VLD1d32wb_fixed: 2308 case ARM::VLD1d64wb_fixed: 2309 case ARM::VLD1d8wb_register: 2310 case ARM::VLD1d16wb_register: 2311 case ARM::VLD1d32wb_register: 2312 case ARM::VLD1d64wb_register: 2313 case ARM::VLD1q8wb_fixed: 2314 case ARM::VLD1q16wb_fixed: 2315 case ARM::VLD1q32wb_fixed: 2316 case ARM::VLD1q64wb_fixed: 2317 case ARM::VLD1q8wb_register: 2318 case ARM::VLD1q16wb_register: 2319 case ARM::VLD1q32wb_register: 2320 case ARM::VLD1q64wb_register: 2321 case ARM::VLD1d8Twb_fixed: 2322 case ARM::VLD1d8Twb_register: 2323 case ARM::VLD1d16Twb_fixed: 2324 case ARM::VLD1d16Twb_register: 2325 case ARM::VLD1d32Twb_fixed: 2326 case ARM::VLD1d32Twb_register: 2327 case ARM::VLD1d64Twb_fixed: 2328 case ARM::VLD1d64Twb_register: 2329 case ARM::VLD1d8Qwb_fixed: 2330 case ARM::VLD1d8Qwb_register: 2331 case ARM::VLD1d16Qwb_fixed: 2332 case ARM::VLD1d16Qwb_register: 2333 case ARM::VLD1d32Qwb_fixed: 2334 case ARM::VLD1d32Qwb_register: 2335 case ARM::VLD1d64Qwb_fixed: 2336 case ARM::VLD1d64Qwb_register: 2337 case ARM::VLD2d8wb_fixed: 2338 case ARM::VLD2d16wb_fixed: 2339 case ARM::VLD2d32wb_fixed: 2340 case ARM::VLD2q8wb_fixed: 2341 case ARM::VLD2q16wb_fixed: 2342 case ARM::VLD2q32wb_fixed: 2343 case ARM::VLD2d8wb_register: 2344 case ARM::VLD2d16wb_register: 2345 case ARM::VLD2d32wb_register: 2346 case ARM::VLD2q8wb_register: 2347 case ARM::VLD2q16wb_register: 2348 case ARM::VLD2q32wb_register: 2349 case ARM::VLD2b8wb_fixed: 2350 case ARM::VLD2b16wb_fixed: 2351 case ARM::VLD2b32wb_fixed: 2352 case ARM::VLD2b8wb_register: 2353 case ARM::VLD2b16wb_register: 2354 case ARM::VLD2b32wb_register: 2355 Inst.addOperand(MCOperand::CreateImm(0)); 2356 break; 2357 case ARM::VLD3d8_UPD: 2358 case ARM::VLD3d16_UPD: 2359 case ARM::VLD3d32_UPD: 2360 case ARM::VLD3q8_UPD: 2361 case ARM::VLD3q16_UPD: 2362 case ARM::VLD3q32_UPD: 2363 case ARM::VLD4d8_UPD: 2364 case ARM::VLD4d16_UPD: 2365 case ARM::VLD4d32_UPD: 2366 case ARM::VLD4q8_UPD: 2367 case ARM::VLD4q16_UPD: 2368 case ARM::VLD4q32_UPD: 2369 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 break; 2372 default: 2373 break; 2374 } 2375 2376 // AddrMode6 Base (register+alignment) 2377 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 2380 // AddrMode6 Offset (register) 2381 switch (Inst.getOpcode()) { 2382 default: 2383 // The below have been updated to have explicit am6offset split 2384 // between fixed and register offset. For those instructions not 2385 // yet updated, we need to add an additional reg0 operand for the 2386 // fixed variant. 2387 // 2388 // The fixed offset encodes as Rm == 0xd, so we check for that. 2389 if (Rm == 0xd) { 2390 Inst.addOperand(MCOperand::CreateReg(0)); 2391 break; 2392 } 2393 // Fall through to handle the register offset variant. 2394 case ARM::VLD1d8wb_fixed: 2395 case ARM::VLD1d16wb_fixed: 2396 case ARM::VLD1d32wb_fixed: 2397 case ARM::VLD1d64wb_fixed: 2398 case ARM::VLD1d8Twb_fixed: 2399 case ARM::VLD1d16Twb_fixed: 2400 case ARM::VLD1d32Twb_fixed: 2401 case ARM::VLD1d64Twb_fixed: 2402 case ARM::VLD1d8Qwb_fixed: 2403 case ARM::VLD1d16Qwb_fixed: 2404 case ARM::VLD1d32Qwb_fixed: 2405 case ARM::VLD1d64Qwb_fixed: 2406 case ARM::VLD1d8wb_register: 2407 case ARM::VLD1d16wb_register: 2408 case ARM::VLD1d32wb_register: 2409 case ARM::VLD1d64wb_register: 2410 case ARM::VLD1q8wb_fixed: 2411 case ARM::VLD1q16wb_fixed: 2412 case ARM::VLD1q32wb_fixed: 2413 case ARM::VLD1q64wb_fixed: 2414 case ARM::VLD1q8wb_register: 2415 case ARM::VLD1q16wb_register: 2416 case ARM::VLD1q32wb_register: 2417 case ARM::VLD1q64wb_register: 2418 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2419 // variant encodes Rm == 0xf. Anything else is a register offset post- 2420 // increment and we need to add the register operand to the instruction. 2421 if (Rm != 0xD && Rm != 0xF && 2422 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2423 return MCDisassembler::Fail; 2424 break; 2425 case ARM::VLD2d8wb_fixed: 2426 case ARM::VLD2d16wb_fixed: 2427 case ARM::VLD2d32wb_fixed: 2428 case ARM::VLD2b8wb_fixed: 2429 case ARM::VLD2b16wb_fixed: 2430 case ARM::VLD2b32wb_fixed: 2431 case ARM::VLD2q8wb_fixed: 2432 case ARM::VLD2q16wb_fixed: 2433 case ARM::VLD2q32wb_fixed: 2434 break; 2435 } 2436 2437 return S; 2438 } 2439 2440 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2441 uint64_t Address, const void *Decoder) { 2442 DecodeStatus S = MCDisassembler::Success; 2443 2444 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2445 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2446 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2447 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2448 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2450 2451 // Writeback Operand 2452 switch (Inst.getOpcode()) { 2453 case ARM::VST1d8wb_fixed: 2454 case ARM::VST1d16wb_fixed: 2455 case ARM::VST1d32wb_fixed: 2456 case ARM::VST1d64wb_fixed: 2457 case ARM::VST1d8wb_register: 2458 case ARM::VST1d16wb_register: 2459 case ARM::VST1d32wb_register: 2460 case ARM::VST1d64wb_register: 2461 case ARM::VST1q8wb_fixed: 2462 case ARM::VST1q16wb_fixed: 2463 case ARM::VST1q32wb_fixed: 2464 case ARM::VST1q64wb_fixed: 2465 case ARM::VST1q8wb_register: 2466 case ARM::VST1q16wb_register: 2467 case ARM::VST1q32wb_register: 2468 case ARM::VST1q64wb_register: 2469 case ARM::VST1d8Twb_fixed: 2470 case ARM::VST1d16Twb_fixed: 2471 case ARM::VST1d32Twb_fixed: 2472 case ARM::VST1d64Twb_fixed: 2473 case ARM::VST1d8Twb_register: 2474 case ARM::VST1d16Twb_register: 2475 case ARM::VST1d32Twb_register: 2476 case ARM::VST1d64Twb_register: 2477 case ARM::VST1d8Qwb_fixed: 2478 case ARM::VST1d16Qwb_fixed: 2479 case ARM::VST1d32Qwb_fixed: 2480 case ARM::VST1d64Qwb_fixed: 2481 case ARM::VST1d8Qwb_register: 2482 case ARM::VST1d16Qwb_register: 2483 case ARM::VST1d32Qwb_register: 2484 case ARM::VST1d64Qwb_register: 2485 case ARM::VST2d8wb_fixed: 2486 case ARM::VST2d16wb_fixed: 2487 case ARM::VST2d32wb_fixed: 2488 case ARM::VST2d8wb_register: 2489 case ARM::VST2d16wb_register: 2490 case ARM::VST2d32wb_register: 2491 case ARM::VST2q8wb_fixed: 2492 case ARM::VST2q16wb_fixed: 2493 case ARM::VST2q32wb_fixed: 2494 case ARM::VST2q8wb_register: 2495 case ARM::VST2q16wb_register: 2496 case ARM::VST2q32wb_register: 2497 case ARM::VST2b8wb_fixed: 2498 case ARM::VST2b16wb_fixed: 2499 case ARM::VST2b32wb_fixed: 2500 case ARM::VST2b8wb_register: 2501 case ARM::VST2b16wb_register: 2502 case ARM::VST2b32wb_register: 2503 if (Rm == 0xF) 2504 return MCDisassembler::Fail; 2505 Inst.addOperand(MCOperand::CreateImm(0)); 2506 break; 2507 case ARM::VST3d8_UPD: 2508 case ARM::VST3d16_UPD: 2509 case ARM::VST3d32_UPD: 2510 case ARM::VST3q8_UPD: 2511 case ARM::VST3q16_UPD: 2512 case ARM::VST3q32_UPD: 2513 case ARM::VST4d8_UPD: 2514 case ARM::VST4d16_UPD: 2515 case ARM::VST4d32_UPD: 2516 case ARM::VST4q8_UPD: 2517 case ARM::VST4q16_UPD: 2518 case ARM::VST4q32_UPD: 2519 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2520 return MCDisassembler::Fail; 2521 break; 2522 default: 2523 break; 2524 } 2525 2526 // AddrMode6 Base (register+alignment) 2527 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 2530 // AddrMode6 Offset (register) 2531 switch (Inst.getOpcode()) { 2532 default: 2533 if (Rm == 0xD) 2534 Inst.addOperand(MCOperand::CreateReg(0)); 2535 else if (Rm != 0xF) { 2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2537 return MCDisassembler::Fail; 2538 } 2539 break; 2540 case ARM::VST1d8wb_fixed: 2541 case ARM::VST1d16wb_fixed: 2542 case ARM::VST1d32wb_fixed: 2543 case ARM::VST1d64wb_fixed: 2544 case ARM::VST1q8wb_fixed: 2545 case ARM::VST1q16wb_fixed: 2546 case ARM::VST1q32wb_fixed: 2547 case ARM::VST1q64wb_fixed: 2548 case ARM::VST1d8Twb_fixed: 2549 case ARM::VST1d16Twb_fixed: 2550 case ARM::VST1d32Twb_fixed: 2551 case ARM::VST1d64Twb_fixed: 2552 case ARM::VST1d8Qwb_fixed: 2553 case ARM::VST1d16Qwb_fixed: 2554 case ARM::VST1d32Qwb_fixed: 2555 case ARM::VST1d64Qwb_fixed: 2556 case ARM::VST2d8wb_fixed: 2557 case ARM::VST2d16wb_fixed: 2558 case ARM::VST2d32wb_fixed: 2559 case ARM::VST2q8wb_fixed: 2560 case ARM::VST2q16wb_fixed: 2561 case ARM::VST2q32wb_fixed: 2562 case ARM::VST2b8wb_fixed: 2563 case ARM::VST2b16wb_fixed: 2564 case ARM::VST2b32wb_fixed: 2565 break; 2566 } 2567 2568 2569 // First input register 2570 switch (Inst.getOpcode()) { 2571 case ARM::VST1q16: 2572 case ARM::VST1q32: 2573 case ARM::VST1q64: 2574 case ARM::VST1q8: 2575 case ARM::VST1q16wb_fixed: 2576 case ARM::VST1q16wb_register: 2577 case ARM::VST1q32wb_fixed: 2578 case ARM::VST1q32wb_register: 2579 case ARM::VST1q64wb_fixed: 2580 case ARM::VST1q64wb_register: 2581 case ARM::VST1q8wb_fixed: 2582 case ARM::VST1q8wb_register: 2583 case ARM::VST2d16: 2584 case ARM::VST2d32: 2585 case ARM::VST2d8: 2586 case ARM::VST2d16wb_fixed: 2587 case ARM::VST2d16wb_register: 2588 case ARM::VST2d32wb_fixed: 2589 case ARM::VST2d32wb_register: 2590 case ARM::VST2d8wb_fixed: 2591 case ARM::VST2d8wb_register: 2592 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2593 return MCDisassembler::Fail; 2594 break; 2595 case ARM::VST2b16: 2596 case ARM::VST2b32: 2597 case ARM::VST2b8: 2598 case ARM::VST2b16wb_fixed: 2599 case ARM::VST2b16wb_register: 2600 case ARM::VST2b32wb_fixed: 2601 case ARM::VST2b32wb_register: 2602 case ARM::VST2b8wb_fixed: 2603 case ARM::VST2b8wb_register: 2604 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 break; 2607 default: 2608 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2609 return MCDisassembler::Fail; 2610 } 2611 2612 // Second input register 2613 switch (Inst.getOpcode()) { 2614 case ARM::VST3d8: 2615 case ARM::VST3d16: 2616 case ARM::VST3d32: 2617 case ARM::VST3d8_UPD: 2618 case ARM::VST3d16_UPD: 2619 case ARM::VST3d32_UPD: 2620 case ARM::VST4d8: 2621 case ARM::VST4d16: 2622 case ARM::VST4d32: 2623 case ARM::VST4d8_UPD: 2624 case ARM::VST4d16_UPD: 2625 case ARM::VST4d32_UPD: 2626 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2627 return MCDisassembler::Fail; 2628 break; 2629 case ARM::VST3q8: 2630 case ARM::VST3q16: 2631 case ARM::VST3q32: 2632 case ARM::VST3q8_UPD: 2633 case ARM::VST3q16_UPD: 2634 case ARM::VST3q32_UPD: 2635 case ARM::VST4q8: 2636 case ARM::VST4q16: 2637 case ARM::VST4q32: 2638 case ARM::VST4q8_UPD: 2639 case ARM::VST4q16_UPD: 2640 case ARM::VST4q32_UPD: 2641 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 break; 2644 default: 2645 break; 2646 } 2647 2648 // Third input register 2649 switch (Inst.getOpcode()) { 2650 case ARM::VST3d8: 2651 case ARM::VST3d16: 2652 case ARM::VST3d32: 2653 case ARM::VST3d8_UPD: 2654 case ARM::VST3d16_UPD: 2655 case ARM::VST3d32_UPD: 2656 case ARM::VST4d8: 2657 case ARM::VST4d16: 2658 case ARM::VST4d32: 2659 case ARM::VST4d8_UPD: 2660 case ARM::VST4d16_UPD: 2661 case ARM::VST4d32_UPD: 2662 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2663 return MCDisassembler::Fail; 2664 break; 2665 case ARM::VST3q8: 2666 case ARM::VST3q16: 2667 case ARM::VST3q32: 2668 case ARM::VST3q8_UPD: 2669 case ARM::VST3q16_UPD: 2670 case ARM::VST3q32_UPD: 2671 case ARM::VST4q8: 2672 case ARM::VST4q16: 2673 case ARM::VST4q32: 2674 case ARM::VST4q8_UPD: 2675 case ARM::VST4q16_UPD: 2676 case ARM::VST4q32_UPD: 2677 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 break; 2680 default: 2681 break; 2682 } 2683 2684 // Fourth input register 2685 switch (Inst.getOpcode()) { 2686 case ARM::VST4d8: 2687 case ARM::VST4d16: 2688 case ARM::VST4d32: 2689 case ARM::VST4d8_UPD: 2690 case ARM::VST4d16_UPD: 2691 case ARM::VST4d32_UPD: 2692 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 break; 2695 case ARM::VST4q8: 2696 case ARM::VST4q16: 2697 case ARM::VST4q32: 2698 case ARM::VST4q8_UPD: 2699 case ARM::VST4q16_UPD: 2700 case ARM::VST4q32_UPD: 2701 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 break; 2704 default: 2705 break; 2706 } 2707 2708 return S; 2709 } 2710 2711 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2712 uint64_t Address, const void *Decoder) { 2713 DecodeStatus S = MCDisassembler::Success; 2714 2715 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2717 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2718 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2719 unsigned align = fieldFromInstruction(Insn, 4, 1); 2720 unsigned size = fieldFromInstruction(Insn, 6, 2); 2721 2722 if (size == 0 && align == 1) 2723 return MCDisassembler::Fail; 2724 align *= (1 << size); 2725 2726 switch (Inst.getOpcode()) { 2727 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2728 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2729 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2730 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2731 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 break; 2734 default: 2735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 } 2739 if (Rm != 0xF) { 2740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 } 2743 2744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 Inst.addOperand(MCOperand::CreateImm(align)); 2747 2748 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2749 // variant encodes Rm == 0xf. Anything else is a register offset post- 2750 // increment and we need to add the register operand to the instruction. 2751 if (Rm != 0xD && Rm != 0xF && 2752 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 2755 return S; 2756 } 2757 2758 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2759 uint64_t Address, const void *Decoder) { 2760 DecodeStatus S = MCDisassembler::Success; 2761 2762 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2763 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2764 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2765 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2766 unsigned align = fieldFromInstruction(Insn, 4, 1); 2767 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2768 align *= 2*size; 2769 2770 switch (Inst.getOpcode()) { 2771 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2772 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2773 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2774 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2775 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2776 return MCDisassembler::Fail; 2777 break; 2778 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2779 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2780 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2781 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2782 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 break; 2785 default: 2786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 break; 2789 } 2790 2791 if (Rm != 0xF) 2792 Inst.addOperand(MCOperand::CreateImm(0)); 2793 2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 Inst.addOperand(MCOperand::CreateImm(align)); 2797 2798 if (Rm != 0xD && Rm != 0xF) { 2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 } 2802 2803 return S; 2804 } 2805 2806 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2807 uint64_t Address, const void *Decoder) { 2808 DecodeStatus S = MCDisassembler::Success; 2809 2810 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2811 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2812 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2813 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2814 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2815 2816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2817 return MCDisassembler::Fail; 2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 if (Rm != 0xF) { 2823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 } 2826 2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 Inst.addOperand(MCOperand::CreateImm(0)); 2830 2831 if (Rm == 0xD) 2832 Inst.addOperand(MCOperand::CreateReg(0)); 2833 else if (Rm != 0xF) { 2834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 } 2837 2838 return S; 2839 } 2840 2841 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2842 uint64_t Address, const void *Decoder) { 2843 DecodeStatus S = MCDisassembler::Success; 2844 2845 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2846 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2848 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2849 unsigned size = fieldFromInstruction(Insn, 6, 2); 2850 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2851 unsigned align = fieldFromInstruction(Insn, 4, 1); 2852 2853 if (size == 0x3) { 2854 if (align == 0) 2855 return MCDisassembler::Fail; 2856 size = 4; 2857 align = 16; 2858 } else { 2859 if (size == 2) { 2860 size = 1 << size; 2861 align *= 8; 2862 } else { 2863 size = 1 << size; 2864 align *= 4*size; 2865 } 2866 } 2867 2868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2871 return MCDisassembler::Fail; 2872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 if (Rm != 0xF) { 2877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 } 2880 2881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2882 return MCDisassembler::Fail; 2883 Inst.addOperand(MCOperand::CreateImm(align)); 2884 2885 if (Rm == 0xD) 2886 Inst.addOperand(MCOperand::CreateReg(0)); 2887 else if (Rm != 0xF) { 2888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2889 return MCDisassembler::Fail; 2890 } 2891 2892 return S; 2893 } 2894 2895 static DecodeStatus 2896 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2897 uint64_t Address, const void *Decoder) { 2898 DecodeStatus S = MCDisassembler::Success; 2899 2900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2902 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2903 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2904 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2905 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2906 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2907 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2908 2909 if (Q) { 2910 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2911 return MCDisassembler::Fail; 2912 } else { 2913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 } 2916 2917 Inst.addOperand(MCOperand::CreateImm(imm)); 2918 2919 switch (Inst.getOpcode()) { 2920 case ARM::VORRiv4i16: 2921 case ARM::VORRiv2i32: 2922 case ARM::VBICiv4i16: 2923 case ARM::VBICiv2i32: 2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 break; 2927 case ARM::VORRiv8i16: 2928 case ARM::VORRiv4i32: 2929 case ARM::VBICiv8i16: 2930 case ARM::VBICiv4i32: 2931 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 break; 2934 default: 2935 break; 2936 } 2937 2938 return S; 2939 } 2940 2941 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2942 uint64_t Address, const void *Decoder) { 2943 DecodeStatus S = MCDisassembler::Success; 2944 2945 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2946 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2947 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2948 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2949 unsigned size = fieldFromInstruction(Insn, 18, 2); 2950 2951 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2952 return MCDisassembler::Fail; 2953 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2954 return MCDisassembler::Fail; 2955 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2956 2957 return S; 2958 } 2959 2960 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2961 uint64_t Address, const void *Decoder) { 2962 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2963 return MCDisassembler::Success; 2964 } 2965 2966 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2967 uint64_t Address, const void *Decoder) { 2968 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2969 return MCDisassembler::Success; 2970 } 2971 2972 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2975 return MCDisassembler::Success; 2976 } 2977 2978 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2979 uint64_t Address, const void *Decoder) { 2980 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2981 return MCDisassembler::Success; 2982 } 2983 2984 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2985 uint64_t Address, const void *Decoder) { 2986 DecodeStatus S = MCDisassembler::Success; 2987 2988 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2989 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2990 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2991 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2992 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2993 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2994 unsigned op = fieldFromInstruction(Insn, 6, 1); 2995 2996 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 if (op) { 2999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3000 return MCDisassembler::Fail; // Writeback 3001 } 3002 3003 switch (Inst.getOpcode()) { 3004 case ARM::VTBL2: 3005 case ARM::VTBX2: 3006 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 break; 3009 default: 3010 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 } 3013 3014 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 3017 return S; 3018 } 3019 3020 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3021 uint64_t Address, const void *Decoder) { 3022 DecodeStatus S = MCDisassembler::Success; 3023 3024 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3025 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3026 3027 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 3030 switch(Inst.getOpcode()) { 3031 default: 3032 return MCDisassembler::Fail; 3033 case ARM::tADR: 3034 break; // tADR does not explicitly represent the PC as an operand. 3035 case ARM::tADDrSPi: 3036 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3037 break; 3038 } 3039 3040 Inst.addOperand(MCOperand::CreateImm(imm)); 3041 return S; 3042 } 3043 3044 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3045 uint64_t Address, const void *Decoder) { 3046 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3047 true, 2, Inst, Decoder)) 3048 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3049 return MCDisassembler::Success; 3050 } 3051 3052 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3053 uint64_t Address, const void *Decoder) { 3054 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3055 true, 4, Inst, Decoder)) 3056 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3057 return MCDisassembler::Success; 3058 } 3059 3060 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3061 uint64_t Address, const void *Decoder) { 3062 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 3063 true, 2, Inst, Decoder)) 3064 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 3065 return MCDisassembler::Success; 3066 } 3067 3068 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3069 uint64_t Address, const void *Decoder) { 3070 DecodeStatus S = MCDisassembler::Success; 3071 3072 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3073 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3074 3075 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 3080 return S; 3081 } 3082 3083 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3084 uint64_t Address, const void *Decoder) { 3085 DecodeStatus S = MCDisassembler::Success; 3086 3087 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3088 unsigned imm = fieldFromInstruction(Val, 3, 5); 3089 3090 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 Inst.addOperand(MCOperand::CreateImm(imm)); 3093 3094 return S; 3095 } 3096 3097 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3098 uint64_t Address, const void *Decoder) { 3099 unsigned imm = Val << 2; 3100 3101 Inst.addOperand(MCOperand::CreateImm(imm)); 3102 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3103 3104 return MCDisassembler::Success; 3105 } 3106 3107 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3108 uint64_t Address, const void *Decoder) { 3109 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3110 Inst.addOperand(MCOperand::CreateImm(Val)); 3111 3112 return MCDisassembler::Success; 3113 } 3114 3115 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = MCDisassembler::Success; 3118 3119 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3120 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3121 unsigned imm = fieldFromInstruction(Val, 0, 2); 3122 3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3126 return MCDisassembler::Fail; 3127 Inst.addOperand(MCOperand::CreateImm(imm)); 3128 3129 return S; 3130 } 3131 3132 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3133 uint64_t Address, const void *Decoder) { 3134 DecodeStatus S = MCDisassembler::Success; 3135 3136 switch (Inst.getOpcode()) { 3137 case ARM::t2PLDs: 3138 case ARM::t2PLDWs: 3139 case ARM::t2PLIs: 3140 break; 3141 default: { 3142 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3143 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3144 return MCDisassembler::Fail; 3145 } 3146 } 3147 3148 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3149 if (Rn == 0xF) { 3150 switch (Inst.getOpcode()) { 3151 case ARM::t2LDRBs: 3152 Inst.setOpcode(ARM::t2LDRBpci); 3153 break; 3154 case ARM::t2LDRHs: 3155 Inst.setOpcode(ARM::t2LDRHpci); 3156 break; 3157 case ARM::t2LDRSHs: 3158 Inst.setOpcode(ARM::t2LDRSHpci); 3159 break; 3160 case ARM::t2LDRSBs: 3161 Inst.setOpcode(ARM::t2LDRSBpci); 3162 break; 3163 case ARM::t2PLDs: 3164 Inst.setOpcode(ARM::t2PLDi12); 3165 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3166 break; 3167 default: 3168 return MCDisassembler::Fail; 3169 } 3170 3171 int imm = fieldFromInstruction(Insn, 0, 12); 3172 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3173 Inst.addOperand(MCOperand::CreateImm(imm)); 3174 3175 return S; 3176 } 3177 3178 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3179 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3180 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3181 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 3184 return S; 3185 } 3186 3187 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3188 uint64_t Address, const void *Decoder) { 3189 if (Val == 0) 3190 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3191 else { 3192 int imm = Val & 0xFF; 3193 3194 if (!(Val & 0x100)) imm *= -1; 3195 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3196 } 3197 3198 return MCDisassembler::Success; 3199 } 3200 3201 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3202 uint64_t Address, const void *Decoder) { 3203 DecodeStatus S = MCDisassembler::Success; 3204 3205 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3206 unsigned imm = fieldFromInstruction(Val, 0, 9); 3207 3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3209 return MCDisassembler::Fail; 3210 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3211 return MCDisassembler::Fail; 3212 3213 return S; 3214 } 3215 3216 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3217 uint64_t Address, const void *Decoder) { 3218 DecodeStatus S = MCDisassembler::Success; 3219 3220 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3221 unsigned imm = fieldFromInstruction(Val, 0, 8); 3222 3223 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 3226 Inst.addOperand(MCOperand::CreateImm(imm)); 3227 3228 return S; 3229 } 3230 3231 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3232 uint64_t Address, const void *Decoder) { 3233 int imm = Val & 0xFF; 3234 if (Val == 0) 3235 imm = INT32_MIN; 3236 else if (!(Val & 0x100)) 3237 imm *= -1; 3238 Inst.addOperand(MCOperand::CreateImm(imm)); 3239 3240 return MCDisassembler::Success; 3241 } 3242 3243 3244 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3245 uint64_t Address, const void *Decoder) { 3246 DecodeStatus S = MCDisassembler::Success; 3247 3248 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3249 unsigned imm = fieldFromInstruction(Val, 0, 9); 3250 3251 // Some instructions always use an additive offset. 3252 switch (Inst.getOpcode()) { 3253 case ARM::t2LDRT: 3254 case ARM::t2LDRBT: 3255 case ARM::t2LDRHT: 3256 case ARM::t2LDRSBT: 3257 case ARM::t2LDRSHT: 3258 case ARM::t2STRT: 3259 case ARM::t2STRBT: 3260 case ARM::t2STRHT: 3261 imm |= 0x100; 3262 break; 3263 default: 3264 break; 3265 } 3266 3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 3272 return S; 3273 } 3274 3275 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3276 uint64_t Address, const void *Decoder) { 3277 DecodeStatus S = MCDisassembler::Success; 3278 3279 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3280 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3281 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3282 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3283 addr |= Rn << 9; 3284 unsigned load = fieldFromInstruction(Insn, 20, 1); 3285 3286 if (!load) { 3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3288 return MCDisassembler::Fail; 3289 } 3290 3291 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 3294 if (load) { 3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 } 3298 3299 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 3302 return S; 3303 } 3304 3305 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3306 uint64_t Address, const void *Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3310 unsigned imm = fieldFromInstruction(Val, 0, 12); 3311 3312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 Inst.addOperand(MCOperand::CreateImm(imm)); 3315 3316 return S; 3317 } 3318 3319 3320 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3321 uint64_t Address, const void *Decoder) { 3322 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3323 3324 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3325 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3326 Inst.addOperand(MCOperand::CreateImm(imm)); 3327 3328 return MCDisassembler::Success; 3329 } 3330 3331 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3332 uint64_t Address, const void *Decoder) { 3333 DecodeStatus S = MCDisassembler::Success; 3334 3335 if (Inst.getOpcode() == ARM::tADDrSP) { 3336 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3337 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3338 3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3340 return MCDisassembler::Fail; 3341 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 } else if (Inst.getOpcode() == ARM::tADDspr) { 3345 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3346 3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3348 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 } 3352 3353 return S; 3354 } 3355 3356 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3357 uint64_t Address, const void *Decoder) { 3358 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3359 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3360 3361 Inst.addOperand(MCOperand::CreateImm(imod)); 3362 Inst.addOperand(MCOperand::CreateImm(flags)); 3363 3364 return MCDisassembler::Success; 3365 } 3366 3367 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3368 uint64_t Address, const void *Decoder) { 3369 DecodeStatus S = MCDisassembler::Success; 3370 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3371 unsigned add = fieldFromInstruction(Insn, 4, 1); 3372 3373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 Inst.addOperand(MCOperand::CreateImm(add)); 3376 3377 return S; 3378 } 3379 3380 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3381 uint64_t Address, const void *Decoder) { 3382 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3383 // Note only one trailing zero not two. Also the J1 and J2 values are from 3384 // the encoded instruction. So here change to I1 and I2 values via: 3385 // I1 = NOT(J1 EOR S); 3386 // I2 = NOT(J2 EOR S); 3387 // and build the imm32 with two trailing zeros as documented: 3388 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3389 unsigned S = (Val >> 23) & 1; 3390 unsigned J1 = (Val >> 22) & 1; 3391 unsigned J2 = (Val >> 21) & 1; 3392 unsigned I1 = !(J1 ^ S); 3393 unsigned I2 = !(J2 ^ S); 3394 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3395 int imm32 = SignExtend32<25>(tmp << 1); 3396 3397 if (!tryAddingSymbolicOperand(Address, 3398 (Address & ~2u) + imm32 + 4, 3399 true, 4, Inst, Decoder)) 3400 Inst.addOperand(MCOperand::CreateImm(imm32)); 3401 return MCDisassembler::Success; 3402 } 3403 3404 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3405 uint64_t Address, const void *Decoder) { 3406 if (Val == 0xA || Val == 0xB) 3407 return MCDisassembler::Fail; 3408 3409 Inst.addOperand(MCOperand::CreateImm(Val)); 3410 return MCDisassembler::Success; 3411 } 3412 3413 static DecodeStatus 3414 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3415 uint64_t Address, const void *Decoder) { 3416 DecodeStatus S = MCDisassembler::Success; 3417 3418 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3419 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3420 3421 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 return S; 3427 } 3428 3429 static DecodeStatus 3430 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3431 uint64_t Address, const void *Decoder) { 3432 DecodeStatus S = MCDisassembler::Success; 3433 3434 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3435 if (pred == 0xE || pred == 0xF) { 3436 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3437 switch (opc) { 3438 default: 3439 return MCDisassembler::Fail; 3440 case 0xf3bf8f4: 3441 Inst.setOpcode(ARM::t2DSB); 3442 break; 3443 case 0xf3bf8f5: 3444 Inst.setOpcode(ARM::t2DMB); 3445 break; 3446 case 0xf3bf8f6: 3447 Inst.setOpcode(ARM::t2ISB); 3448 break; 3449 } 3450 3451 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3452 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3453 } 3454 3455 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3456 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3457 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3458 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3459 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3460 3461 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3464 return MCDisassembler::Fail; 3465 3466 return S; 3467 } 3468 3469 // Decode a shifted immediate operand. These basically consist 3470 // of an 8-bit value, and a 4-bit directive that specifies either 3471 // a splat operation or a rotation. 3472 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3473 uint64_t Address, const void *Decoder) { 3474 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3475 if (ctrl == 0) { 3476 unsigned byte = fieldFromInstruction(Val, 8, 2); 3477 unsigned imm = fieldFromInstruction(Val, 0, 8); 3478 switch (byte) { 3479 case 0: 3480 Inst.addOperand(MCOperand::CreateImm(imm)); 3481 break; 3482 case 1: 3483 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3484 break; 3485 case 2: 3486 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3487 break; 3488 case 3: 3489 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3490 (imm << 8) | imm)); 3491 break; 3492 } 3493 } else { 3494 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3495 unsigned rot = fieldFromInstruction(Val, 7, 5); 3496 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3497 Inst.addOperand(MCOperand::CreateImm(imm)); 3498 } 3499 3500 return MCDisassembler::Success; 3501 } 3502 3503 static DecodeStatus 3504 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3505 uint64_t Address, const void *Decoder){ 3506 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3507 true, 2, Inst, Decoder)) 3508 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3509 return MCDisassembler::Success; 3510 } 3511 3512 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3513 uint64_t Address, const void *Decoder){ 3514 // Val is passed in as S:J1:J2:imm10:imm11 3515 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3516 // the encoded instruction. So here change to I1 and I2 values via: 3517 // I1 = NOT(J1 EOR S); 3518 // I2 = NOT(J2 EOR S); 3519 // and build the imm32 with one trailing zero as documented: 3520 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3521 unsigned S = (Val >> 23) & 1; 3522 unsigned J1 = (Val >> 22) & 1; 3523 unsigned J2 = (Val >> 21) & 1; 3524 unsigned I1 = !(J1 ^ S); 3525 unsigned I2 = !(J2 ^ S); 3526 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3527 int imm32 = SignExtend32<25>(tmp << 1); 3528 3529 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3530 true, 4, Inst, Decoder)) 3531 Inst.addOperand(MCOperand::CreateImm(imm32)); 3532 return MCDisassembler::Success; 3533 } 3534 3535 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3536 uint64_t Address, const void *Decoder) { 3537 if (Val & ~0xf) 3538 return MCDisassembler::Fail; 3539 3540 Inst.addOperand(MCOperand::CreateImm(Val)); 3541 return MCDisassembler::Success; 3542 } 3543 3544 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3545 uint64_t Address, const void *Decoder) { 3546 if (!Val) return MCDisassembler::Fail; 3547 Inst.addOperand(MCOperand::CreateImm(Val)); 3548 return MCDisassembler::Success; 3549 } 3550 3551 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3552 uint64_t Address, const void *Decoder) { 3553 DecodeStatus S = MCDisassembler::Success; 3554 3555 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3556 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3557 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3558 3559 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3560 3561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 3570 return S; 3571 } 3572 3573 3574 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3575 uint64_t Address, const void *Decoder){ 3576 DecodeStatus S = MCDisassembler::Success; 3577 3578 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3579 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3581 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3582 3583 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3584 return MCDisassembler::Fail; 3585 3586 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3587 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3588 3589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3590 return MCDisassembler::Fail; 3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 3598 return S; 3599 } 3600 3601 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3602 uint64_t Address, const void *Decoder) { 3603 DecodeStatus S = MCDisassembler::Success; 3604 3605 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3606 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3607 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3608 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3609 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3610 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3611 3612 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3613 3614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 3623 return S; 3624 } 3625 3626 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3627 uint64_t Address, const void *Decoder) { 3628 DecodeStatus S = MCDisassembler::Success; 3629 3630 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3631 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3632 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3633 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3634 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3635 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3636 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3637 3638 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3639 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3640 3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 3650 return S; 3651 } 3652 3653 3654 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3655 uint64_t Address, const void *Decoder) { 3656 DecodeStatus S = MCDisassembler::Success; 3657 3658 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3659 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3660 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3661 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3662 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3663 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3664 3665 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3666 3667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3668 return MCDisassembler::Fail; 3669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3670 return MCDisassembler::Fail; 3671 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 3676 return S; 3677 } 3678 3679 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3680 uint64_t Address, const void *Decoder) { 3681 DecodeStatus S = MCDisassembler::Success; 3682 3683 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3684 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3685 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3686 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3687 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3688 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3689 3690 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3691 3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 3701 return S; 3702 } 3703 3704 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3705 uint64_t Address, const void *Decoder) { 3706 DecodeStatus S = MCDisassembler::Success; 3707 3708 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3709 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3711 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3712 unsigned size = fieldFromInstruction(Insn, 10, 2); 3713 3714 unsigned align = 0; 3715 unsigned index = 0; 3716 switch (size) { 3717 default: 3718 return MCDisassembler::Fail; 3719 case 0: 3720 if (fieldFromInstruction(Insn, 4, 1)) 3721 return MCDisassembler::Fail; // UNDEFINED 3722 index = fieldFromInstruction(Insn, 5, 3); 3723 break; 3724 case 1: 3725 if (fieldFromInstruction(Insn, 5, 1)) 3726 return MCDisassembler::Fail; // UNDEFINED 3727 index = fieldFromInstruction(Insn, 6, 2); 3728 if (fieldFromInstruction(Insn, 4, 1)) 3729 align = 2; 3730 break; 3731 case 2: 3732 if (fieldFromInstruction(Insn, 6, 1)) 3733 return MCDisassembler::Fail; // UNDEFINED 3734 index = fieldFromInstruction(Insn, 7, 1); 3735 3736 switch (fieldFromInstruction(Insn, 4, 2)) { 3737 case 0 : 3738 align = 0; break; 3739 case 3: 3740 align = 4; break; 3741 default: 3742 return MCDisassembler::Fail; 3743 } 3744 break; 3745 } 3746 3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 if (Rm != 0xF) { // Writeback 3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 } 3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 Inst.addOperand(MCOperand::CreateImm(align)); 3756 if (Rm != 0xF) { 3757 if (Rm != 0xD) { 3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 } else 3761 Inst.addOperand(MCOperand::CreateReg(0)); 3762 } 3763 3764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 Inst.addOperand(MCOperand::CreateImm(index)); 3767 3768 return S; 3769 } 3770 3771 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3772 uint64_t Address, const void *Decoder) { 3773 DecodeStatus S = MCDisassembler::Success; 3774 3775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3776 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3777 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3778 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3779 unsigned size = fieldFromInstruction(Insn, 10, 2); 3780 3781 unsigned align = 0; 3782 unsigned index = 0; 3783 switch (size) { 3784 default: 3785 return MCDisassembler::Fail; 3786 case 0: 3787 if (fieldFromInstruction(Insn, 4, 1)) 3788 return MCDisassembler::Fail; // UNDEFINED 3789 index = fieldFromInstruction(Insn, 5, 3); 3790 break; 3791 case 1: 3792 if (fieldFromInstruction(Insn, 5, 1)) 3793 return MCDisassembler::Fail; // UNDEFINED 3794 index = fieldFromInstruction(Insn, 6, 2); 3795 if (fieldFromInstruction(Insn, 4, 1)) 3796 align = 2; 3797 break; 3798 case 2: 3799 if (fieldFromInstruction(Insn, 6, 1)) 3800 return MCDisassembler::Fail; // UNDEFINED 3801 index = fieldFromInstruction(Insn, 7, 1); 3802 3803 switch (fieldFromInstruction(Insn, 4, 2)) { 3804 case 0: 3805 align = 0; break; 3806 case 3: 3807 align = 4; break; 3808 default: 3809 return MCDisassembler::Fail; 3810 } 3811 break; 3812 } 3813 3814 if (Rm != 0xF) { // Writeback 3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 } 3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 Inst.addOperand(MCOperand::CreateImm(align)); 3821 if (Rm != 0xF) { 3822 if (Rm != 0xD) { 3823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 } else 3826 Inst.addOperand(MCOperand::CreateReg(0)); 3827 } 3828 3829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 Inst.addOperand(MCOperand::CreateImm(index)); 3832 3833 return S; 3834 } 3835 3836 3837 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3838 uint64_t Address, const void *Decoder) { 3839 DecodeStatus S = MCDisassembler::Success; 3840 3841 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3842 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3843 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3844 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3845 unsigned size = fieldFromInstruction(Insn, 10, 2); 3846 3847 unsigned align = 0; 3848 unsigned index = 0; 3849 unsigned inc = 1; 3850 switch (size) { 3851 default: 3852 return MCDisassembler::Fail; 3853 case 0: 3854 index = fieldFromInstruction(Insn, 5, 3); 3855 if (fieldFromInstruction(Insn, 4, 1)) 3856 align = 2; 3857 break; 3858 case 1: 3859 index = fieldFromInstruction(Insn, 6, 2); 3860 if (fieldFromInstruction(Insn, 4, 1)) 3861 align = 4; 3862 if (fieldFromInstruction(Insn, 5, 1)) 3863 inc = 2; 3864 break; 3865 case 2: 3866 if (fieldFromInstruction(Insn, 5, 1)) 3867 return MCDisassembler::Fail; // UNDEFINED 3868 index = fieldFromInstruction(Insn, 7, 1); 3869 if (fieldFromInstruction(Insn, 4, 1) != 0) 3870 align = 8; 3871 if (fieldFromInstruction(Insn, 6, 1)) 3872 inc = 2; 3873 break; 3874 } 3875 3876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 if (Rm != 0xF) { // Writeback 3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 } 3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 Inst.addOperand(MCOperand::CreateImm(align)); 3887 if (Rm != 0xF) { 3888 if (Rm != 0xD) { 3889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 } else 3892 Inst.addOperand(MCOperand::CreateReg(0)); 3893 } 3894 3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 Inst.addOperand(MCOperand::CreateImm(index)); 3900 3901 return S; 3902 } 3903 3904 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3905 uint64_t Address, const void *Decoder) { 3906 DecodeStatus S = MCDisassembler::Success; 3907 3908 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3909 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3910 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3911 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3912 unsigned size = fieldFromInstruction(Insn, 10, 2); 3913 3914 unsigned align = 0; 3915 unsigned index = 0; 3916 unsigned inc = 1; 3917 switch (size) { 3918 default: 3919 return MCDisassembler::Fail; 3920 case 0: 3921 index = fieldFromInstruction(Insn, 5, 3); 3922 if (fieldFromInstruction(Insn, 4, 1)) 3923 align = 2; 3924 break; 3925 case 1: 3926 index = fieldFromInstruction(Insn, 6, 2); 3927 if (fieldFromInstruction(Insn, 4, 1)) 3928 align = 4; 3929 if (fieldFromInstruction(Insn, 5, 1)) 3930 inc = 2; 3931 break; 3932 case 2: 3933 if (fieldFromInstruction(Insn, 5, 1)) 3934 return MCDisassembler::Fail; // UNDEFINED 3935 index = fieldFromInstruction(Insn, 7, 1); 3936 if (fieldFromInstruction(Insn, 4, 1) != 0) 3937 align = 8; 3938 if (fieldFromInstruction(Insn, 6, 1)) 3939 inc = 2; 3940 break; 3941 } 3942 3943 if (Rm != 0xF) { // Writeback 3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 } 3947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3948 return MCDisassembler::Fail; 3949 Inst.addOperand(MCOperand::CreateImm(align)); 3950 if (Rm != 0xF) { 3951 if (Rm != 0xD) { 3952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 } else 3955 Inst.addOperand(MCOperand::CreateReg(0)); 3956 } 3957 3958 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3959 return MCDisassembler::Fail; 3960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3961 return MCDisassembler::Fail; 3962 Inst.addOperand(MCOperand::CreateImm(index)); 3963 3964 return S; 3965 } 3966 3967 3968 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3969 uint64_t Address, const void *Decoder) { 3970 DecodeStatus S = MCDisassembler::Success; 3971 3972 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3973 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3974 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3975 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3976 unsigned size = fieldFromInstruction(Insn, 10, 2); 3977 3978 unsigned align = 0; 3979 unsigned index = 0; 3980 unsigned inc = 1; 3981 switch (size) { 3982 default: 3983 return MCDisassembler::Fail; 3984 case 0: 3985 if (fieldFromInstruction(Insn, 4, 1)) 3986 return MCDisassembler::Fail; // UNDEFINED 3987 index = fieldFromInstruction(Insn, 5, 3); 3988 break; 3989 case 1: 3990 if (fieldFromInstruction(Insn, 4, 1)) 3991 return MCDisassembler::Fail; // UNDEFINED 3992 index = fieldFromInstruction(Insn, 6, 2); 3993 if (fieldFromInstruction(Insn, 5, 1)) 3994 inc = 2; 3995 break; 3996 case 2: 3997 if (fieldFromInstruction(Insn, 4, 2)) 3998 return MCDisassembler::Fail; // UNDEFINED 3999 index = fieldFromInstruction(Insn, 7, 1); 4000 if (fieldFromInstruction(Insn, 6, 1)) 4001 inc = 2; 4002 break; 4003 } 4004 4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 4012 if (Rm != 0xF) { // Writeback 4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 } 4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 Inst.addOperand(MCOperand::CreateImm(align)); 4019 if (Rm != 0xF) { 4020 if (Rm != 0xD) { 4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 } else 4024 Inst.addOperand(MCOperand::CreateReg(0)); 4025 } 4026 4027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 Inst.addOperand(MCOperand::CreateImm(index)); 4034 4035 return S; 4036 } 4037 4038 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4039 uint64_t Address, const void *Decoder) { 4040 DecodeStatus S = MCDisassembler::Success; 4041 4042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4043 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4044 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4045 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4046 unsigned size = fieldFromInstruction(Insn, 10, 2); 4047 4048 unsigned align = 0; 4049 unsigned index = 0; 4050 unsigned inc = 1; 4051 switch (size) { 4052 default: 4053 return MCDisassembler::Fail; 4054 case 0: 4055 if (fieldFromInstruction(Insn, 4, 1)) 4056 return MCDisassembler::Fail; // UNDEFINED 4057 index = fieldFromInstruction(Insn, 5, 3); 4058 break; 4059 case 1: 4060 if (fieldFromInstruction(Insn, 4, 1)) 4061 return MCDisassembler::Fail; // UNDEFINED 4062 index = fieldFromInstruction(Insn, 6, 2); 4063 if (fieldFromInstruction(Insn, 5, 1)) 4064 inc = 2; 4065 break; 4066 case 2: 4067 if (fieldFromInstruction(Insn, 4, 2)) 4068 return MCDisassembler::Fail; // UNDEFINED 4069 index = fieldFromInstruction(Insn, 7, 1); 4070 if (fieldFromInstruction(Insn, 6, 1)) 4071 inc = 2; 4072 break; 4073 } 4074 4075 if (Rm != 0xF) { // Writeback 4076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4077 return MCDisassembler::Fail; 4078 } 4079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 Inst.addOperand(MCOperand::CreateImm(align)); 4082 if (Rm != 0xF) { 4083 if (Rm != 0xD) { 4084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 } else 4087 Inst.addOperand(MCOperand::CreateReg(0)); 4088 } 4089 4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4095 return MCDisassembler::Fail; 4096 Inst.addOperand(MCOperand::CreateImm(index)); 4097 4098 return S; 4099 } 4100 4101 4102 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4103 uint64_t Address, const void *Decoder) { 4104 DecodeStatus S = MCDisassembler::Success; 4105 4106 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4107 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4108 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4109 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4110 unsigned size = fieldFromInstruction(Insn, 10, 2); 4111 4112 unsigned align = 0; 4113 unsigned index = 0; 4114 unsigned inc = 1; 4115 switch (size) { 4116 default: 4117 return MCDisassembler::Fail; 4118 case 0: 4119 if (fieldFromInstruction(Insn, 4, 1)) 4120 align = 4; 4121 index = fieldFromInstruction(Insn, 5, 3); 4122 break; 4123 case 1: 4124 if (fieldFromInstruction(Insn, 4, 1)) 4125 align = 8; 4126 index = fieldFromInstruction(Insn, 6, 2); 4127 if (fieldFromInstruction(Insn, 5, 1)) 4128 inc = 2; 4129 break; 4130 case 2: 4131 switch (fieldFromInstruction(Insn, 4, 2)) { 4132 case 0: 4133 align = 0; break; 4134 case 3: 4135 return MCDisassembler::Fail; 4136 default: 4137 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4138 } 4139 4140 index = fieldFromInstruction(Insn, 7, 1); 4141 if (fieldFromInstruction(Insn, 6, 1)) 4142 inc = 2; 4143 break; 4144 } 4145 4146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4151 return MCDisassembler::Fail; 4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 if (Rm != 0xF) { // Writeback 4156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 } 4159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 Inst.addOperand(MCOperand::CreateImm(align)); 4162 if (Rm != 0xF) { 4163 if (Rm != 0xD) { 4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 } else 4167 Inst.addOperand(MCOperand::CreateReg(0)); 4168 } 4169 4170 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4173 return MCDisassembler::Fail; 4174 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4175 return MCDisassembler::Fail; 4176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4177 return MCDisassembler::Fail; 4178 Inst.addOperand(MCOperand::CreateImm(index)); 4179 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4184 uint64_t Address, const void *Decoder) { 4185 DecodeStatus S = MCDisassembler::Success; 4186 4187 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4188 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4189 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4190 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4191 unsigned size = fieldFromInstruction(Insn, 10, 2); 4192 4193 unsigned align = 0; 4194 unsigned index = 0; 4195 unsigned inc = 1; 4196 switch (size) { 4197 default: 4198 return MCDisassembler::Fail; 4199 case 0: 4200 if (fieldFromInstruction(Insn, 4, 1)) 4201 align = 4; 4202 index = fieldFromInstruction(Insn, 5, 3); 4203 break; 4204 case 1: 4205 if (fieldFromInstruction(Insn, 4, 1)) 4206 align = 8; 4207 index = fieldFromInstruction(Insn, 6, 2); 4208 if (fieldFromInstruction(Insn, 5, 1)) 4209 inc = 2; 4210 break; 4211 case 2: 4212 switch (fieldFromInstruction(Insn, 4, 2)) { 4213 case 0: 4214 align = 0; break; 4215 case 3: 4216 return MCDisassembler::Fail; 4217 default: 4218 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4219 } 4220 4221 index = fieldFromInstruction(Insn, 7, 1); 4222 if (fieldFromInstruction(Insn, 6, 1)) 4223 inc = 2; 4224 break; 4225 } 4226 4227 if (Rm != 0xF) { // Writeback 4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 } 4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4232 return MCDisassembler::Fail; 4233 Inst.addOperand(MCOperand::CreateImm(align)); 4234 if (Rm != 0xF) { 4235 if (Rm != 0xD) { 4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 } else 4239 Inst.addOperand(MCOperand::CreateReg(0)); 4240 } 4241 4242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4247 return MCDisassembler::Fail; 4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 Inst.addOperand(MCOperand::CreateImm(index)); 4251 4252 return S; 4253 } 4254 4255 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4256 uint64_t Address, const void *Decoder) { 4257 DecodeStatus S = MCDisassembler::Success; 4258 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4259 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4260 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4261 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4262 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4263 4264 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4265 S = MCDisassembler::SoftFail; 4266 4267 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4274 return MCDisassembler::Fail; 4275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4276 return MCDisassembler::Fail; 4277 4278 return S; 4279 } 4280 4281 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4282 uint64_t Address, const void *Decoder) { 4283 DecodeStatus S = MCDisassembler::Success; 4284 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4285 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4286 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4287 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4288 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4289 4290 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4291 S = MCDisassembler::SoftFail; 4292 4293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4296 return MCDisassembler::Fail; 4297 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 4304 return S; 4305 } 4306 4307 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4308 uint64_t Address, const void *Decoder) { 4309 DecodeStatus S = MCDisassembler::Success; 4310 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4311 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4312 4313 if (pred == 0xF) { 4314 pred = 0xE; 4315 S = MCDisassembler::SoftFail; 4316 } 4317 4318 if (mask == 0x0) { 4319 mask |= 0x8; 4320 S = MCDisassembler::SoftFail; 4321 } 4322 4323 Inst.addOperand(MCOperand::CreateImm(pred)); 4324 Inst.addOperand(MCOperand::CreateImm(mask)); 4325 return S; 4326 } 4327 4328 static DecodeStatus 4329 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4330 uint64_t Address, const void *Decoder) { 4331 DecodeStatus S = MCDisassembler::Success; 4332 4333 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4334 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4335 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4336 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4337 unsigned W = fieldFromInstruction(Insn, 21, 1); 4338 unsigned U = fieldFromInstruction(Insn, 23, 1); 4339 unsigned P = fieldFromInstruction(Insn, 24, 1); 4340 bool writeback = (W == 1) | (P == 0); 4341 4342 addr |= (U << 8) | (Rn << 9); 4343 4344 if (writeback && (Rn == Rt || Rn == Rt2)) 4345 Check(S, MCDisassembler::SoftFail); 4346 if (Rt == Rt2) 4347 Check(S, MCDisassembler::SoftFail); 4348 4349 // Rt 4350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 // Rt2 4353 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4354 return MCDisassembler::Fail; 4355 // Writeback operand 4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 // addr 4359 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 4362 return S; 4363 } 4364 4365 static DecodeStatus 4366 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4367 uint64_t Address, const void *Decoder) { 4368 DecodeStatus S = MCDisassembler::Success; 4369 4370 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4371 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4372 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4373 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4374 unsigned W = fieldFromInstruction(Insn, 21, 1); 4375 unsigned U = fieldFromInstruction(Insn, 23, 1); 4376 unsigned P = fieldFromInstruction(Insn, 24, 1); 4377 bool writeback = (W == 1) | (P == 0); 4378 4379 addr |= (U << 8) | (Rn << 9); 4380 4381 if (writeback && (Rn == Rt || Rn == Rt2)) 4382 Check(S, MCDisassembler::SoftFail); 4383 4384 // Writeback operand 4385 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4386 return MCDisassembler::Fail; 4387 // Rt 4388 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4389 return MCDisassembler::Fail; 4390 // Rt2 4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 // addr 4394 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 4397 return S; 4398 } 4399 4400 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4401 uint64_t Address, const void *Decoder) { 4402 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4403 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4404 if (sign1 != sign2) return MCDisassembler::Fail; 4405 4406 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4407 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4408 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4409 Val |= sign1 << 12; 4410 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4411 4412 return MCDisassembler::Success; 4413 } 4414 4415 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4416 uint64_t Address, 4417 const void *Decoder) { 4418 DecodeStatus S = MCDisassembler::Success; 4419 4420 // Shift of "asr #32" is not allowed in Thumb2 mode. 4421 if (Val == 0x20) S = MCDisassembler::SoftFail; 4422 Inst.addOperand(MCOperand::CreateImm(Val)); 4423 return S; 4424 } 4425 4426 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4427 uint64_t Address, const void *Decoder) { 4428 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4429 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4430 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4431 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4432 4433 if (pred == 0xF) 4434 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4435 4436 DecodeStatus S = MCDisassembler::Success; 4437 4438 if (Rt == Rn || Rn == Rt2) 4439 S = MCDisassembler::SoftFail; 4440 4441 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4442 return MCDisassembler::Fail; 4443 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4444 return MCDisassembler::Fail; 4445 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4446 return MCDisassembler::Fail; 4447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 4450 return S; 4451 } 4452 4453 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4454 uint64_t Address, const void *Decoder) { 4455 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4456 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4457 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4458 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4459 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4460 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4461 4462 DecodeStatus S = MCDisassembler::Success; 4463 4464 // VMOVv2f32 is ambiguous with these decodings. 4465 if (!(imm & 0x38) && cmode == 0xF) { 4466 Inst.setOpcode(ARM::VMOVv2f32); 4467 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4468 } 4469 4470 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4471 4472 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4473 return MCDisassembler::Fail; 4474 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4475 return MCDisassembler::Fail; 4476 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4477 4478 return S; 4479 } 4480 4481 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4482 uint64_t Address, const void *Decoder) { 4483 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4484 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4485 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4486 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4487 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4488 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4489 4490 DecodeStatus S = MCDisassembler::Success; 4491 4492 // VMOVv4f32 is ambiguous with these decodings. 4493 if (!(imm & 0x38) && cmode == 0xF) { 4494 Inst.setOpcode(ARM::VMOVv4f32); 4495 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4496 } 4497 4498 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4499 4500 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4501 return MCDisassembler::Fail; 4502 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4505 4506 return S; 4507 } 4508 4509 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4510 uint64_t Address, const void *Decoder) { 4511 DecodeStatus S = MCDisassembler::Success; 4512 4513 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4514 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4515 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4516 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4517 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4518 4519 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4520 S = MCDisassembler::SoftFail; 4521 4522 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4523 return MCDisassembler::Fail; 4524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4525 return MCDisassembler::Fail; 4526 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 4533 return S; 4534 } 4535 4536 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4537 uint64_t Address, const void *Decoder) { 4538 4539 DecodeStatus S = MCDisassembler::Success; 4540 4541 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4542 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4543 unsigned cop = fieldFromInstruction(Val, 8, 4); 4544 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4545 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4546 4547 if ((cop & ~0x1) == 0xa) 4548 return MCDisassembler::Fail; 4549 4550 if (Rt == Rt2) 4551 S = MCDisassembler::SoftFail; 4552 4553 Inst.addOperand(MCOperand::CreateImm(cop)); 4554 Inst.addOperand(MCOperand::CreateImm(opc1)); 4555 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 Inst.addOperand(MCOperand::CreateImm(CRm)); 4560 4561 return S; 4562 } 4563 4564